Silly Step7 TEMP question!

at least I hope it's a silly question, but before I make a fool of myself, I'd like to be sure!

Are TEMPs in 4xx CPUs the same as TEMPs in 3xx CPUs, or are they different in some subtle way?

Reason is, I've only worked with 300 series CPUs up till now, but now I've got involved with a 416 CPU where strange things are going on. In the process of looking for possible sources I've fallen over a de-bouncing routine which works by delaying the Input signals for a defined number of 100 ms counts (the 100 ms comes from the on-board Takt-Merker). Typical delay times are between 3 and 5 counts and the current value is held in a TEMP!

Could this be acceptable in a 4xx CPU?

(I'm also a bit puzzled by the fact that there are no flank checks to stop it incrementing its counter every cycle, but maybe I've just not understood the program yet!)

TEMPS are TEMPS are TEMPS are TEMPS no matter what the CPU


(Could be the start to a whacky song !)

That's what I thought, and in the meantime I've discovered that they park the values in a DB in between times - missed that first time through! I'm still struggling to convince myself that the program will actually count 100 ms intervals rather than incrementing every cycle, though, so I may be back!