Anti-reset windup for RSLogix 500.

Hi all,
I've been reading about anti-reset windup. For RSLogix 5000 it seems that the PID block takes cares of it automatically. For RSLogix the situation is different, since this functionality does not exist as a PID block feature.
Therefore, in order to implement a anti-reset windup in the RSLogix 500 code, what would be the best approach? So far, I came up with a logic that sets to 0 the Ti parameter (Integral Gain) of the PID block when the CV (control output) is either 0% or 100%.
In pseudo code: If CV=0% or CV=100% then Ti=0

Is this correct?

Thank you!

The SLC will freeze the integrator when the PV goes outside the proportional band. This causes us problems for our process, so what we do is clear the integrator. We calculate the proportional band and then if the PV goes out side it we one-shot a normally closed bit in the PID rung. This will clear the integrator. I don't know if that's the "right" way, but it works well for us.

You could probably accomplish the same thing by clearing the two words that hold the integrator value. These are the 17th and 18th words in the PID block (if I remember correctly).

Anti-Reset windup can be achieved in RSLogix 500 by Limiting the Output CV because this in turn limits the Integral term from changing when maximum/minimum CV value is reached and thus prevents windup.

You can Limit the Output CV by selecting "Limit Output CV" as "Yes".Then set the limits according to your process.The RSLogix 500 help file extract attached below explains how the PID behaves to the Limits that you set.

Making the rung go false for one scan will clear the integral sum.

Alternately, you can force the integral sum to a particular value by placing the PID in manual mode, setting CV, then place it back in auto mode. We do this for bipolar control of servo valves. You are not limited to a single instance of the PID instruction and you can set up a special routine with another PID instruction to the same address to do this. However in this case you can't condition the PID rung since you don't want the rung to false, so this needs to be in a separate subroutine. I'll post an example later.

I agree with Anirban Hazra post #3. You can write to the CV's % min/max on the fly, your process will dictate. I have done it this way in the past.

I thought I had a line in my previous post about just using the method Anirban mentioned, but looking at it I don't see it. Let me re-emphasize, if all you are doing is limiting it then that is how to do it.

If you are needing to force the integral to some particular value then see the attached ML1100 program.

Thank you everybody for your comments!

Old No. 7 said:

...We calculate the proportional band and then if the PV goes out side it we one-shot a normally closed bit in the PID rung. This will clear the integrator. I don't know if that's the "right" way, but it works well for us.

Click to expand...

OK, but TConnolly, you said:

However in this case you can't condition the PID rung since you don't want the rung to false.

Click to expand...

Why?

You could probably accomplish the same thing by clearing the two words that hold the integrator value. These are the 17th and 18th words in the PID block (if I remember correctly).

Click to expand...

It can be just using MOVE to set PD11:17 and PD11:18 as zero? I would need help on how to write the 17th and 18th words addresses.

I agree with Anirban Hazra post #3. You can write to the CV's % min/max on the fly, your process will dictate. I have done it this way in the past.

Click to expand...

So this will just fix the problem? What will happen with the integral term?

When the SLC500 PID rung is false then the PID instruction clears the integral sum. For this reason the rung should not be conditioned, ie, the PID should not have any logic on the rung in front of it. If conditional execution is required then put it in a conditional subroutine (as shown in my example). Also see technote 15691. There are some rare cases (epmphasis on rare) where you might want to do this, as Old No. 7 does. Even then my personal preference would be to use the method shown in the sample I posted and pick an appropriate CV.

The conditional rung limitation applies only to the SLC and Micrologix platforms. The PID in a PLC/5 or CLX can be on a conditional rung and in fact must be when not in an STI or periodic task.

Elcan said:

So this will just fix the problem? What will happen with the integral term?

Click to expand...

The integral is limited to CVMax and CVMin. It won't get any larger or smaller.


ETA:
In this recent thread http://www.plctalk.net/qanda/showpost.php?p=526127&postcount=6 I talked about setting up a PID for a cooling tower and showed how the PID could be simulated. If you have a PLC that you can play with you might want to try a few things and get a feel for how the SLC PID works.

The solution (limiting the CV) was simpler than I was expecting.

Thank you everybody for the help!