BSL Example

GaryS said:

i an not even sure that will work ... it would be interesting to test it

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I know it works: [OTU R6:0/EN] does the trick*, exactly as shown in post #7; I also tested [OTU control.DN], which does not work

* R6:0 is a control structure in MicroLogix; I have not tested anything else e.g. ControlLogix, but I have seen others use the technique elsewhere, even on other PLC brands

GaryS said:

where are you getting a clock pulse of 10Khz for the free running clock the CPU clock pulse would be closer to 100Mhz and I have confirmed that the S:4/0 changes state every .1 ms that is .00001 sec and with that the value of the word will count up by .1 ms the resolution of the word is .1 ms

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As you note, and the MicroLogix manual confirms**, FRC clock counts 100μs (=0.1ms) periods with the FRC bit-0 transitions:

• 100 μs/bit = 100e-6 s/bit = 1e-4 s/bit
• The reciprocal of that is 1e+4 bit/s = 10e+3 bit/s = 10kHz

** N.B. MicroLogix 1100, 1200, 1500 only; MicroLogix 1000 and SLC 500 are 10ms/bit => 100Hz.

GaryS said:

but why would want to update the BSL on every scan

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I'm only fleshing out how it works; any motivation to use it would almost certainly be rare, but my experience is that techniques like this do come in handy (cf. that youtube clip ).


Also, I did not figure this out on my own but read it elsewhere on this forum (where else?), although it was on a CTU instruction, which is also a rising-edge-triggered and uses the counter structure. Ah, here is a reason: say there is a Selectable Timed Interrupt (STI) routine, and I wanted to increment a counter every time some condition was true in the STI, even if that condition's state did not change between successive STI runs i.e. no rising edge. Obviously an [ADD var 1 var] does the same thing, but the counter has that convenient .DN bit.


Finally, there is a typo in my rising-edge ladder code; I'll fix it in another post ...

At least one of my previous posts (#29) had a mistake; that ladder-equivalent of a one-shot, rising-edge detect should look like this:


In the original post, the [OTL storage_bit] branch was above the [XIO storage_bit OTE rising_edge_bit] branch, so the OTL would execute first, which would keep the XIO in the latter branch from ever evaluating to true.


d'Oh!