rdrast
Lifetime Supporting Member
What would cause the math underflow or overflow errors? I've never really seen many PLC faults before.
Any division by zero, or any other math operation that could cause an overflow or underflow.
Typically, for SLC Programs, as the very last rung of LAD-2, people will put in an unconditional latch of S:5/0 (the math overflow trap bit) to prevent the processor from hard faulting. It only hard faults if that bit is set at the beginning of the program scan.
Whenever unconditionally resetting the overflow trap, I like to include one more rung just above that, so that if S:5/0 is set, I latch another internal bit so that if I'm ever looking online at the program, I can see that an overflow has happened.
All of these fault bits are explained very well in the help files loaded with Logix 500.