Bytronic ICT3 help (LADSIM)

[mrmennell]

So basically im programming for my studys on the ICT3 via ladsim. I have everything sort of working but the method in which i have used for rejection just isn't reliable enough and i don't know how i can further improve it.


I've tried to make the conveyor for OP4 act as a kind of encoder but i think my scan timer for the bit shift isn't good enough but only having 16 bit address im limited.


This is my current layout for the rungs.


Rung 7 - --||IP8--|/|IP3-----( )R1(bit0)
Rung 8 - --||O4(conveyor)--|/|T2------( )T2
Rung 9 - --||T2----------( )R1/0
Rung 10- --|/|R1(bit 8)--||IP5-----( )O3


So what we have in this sequence is IP3 (Ring assembled) High signal and IP8(Belt peg detected) low signal. IP4 is component detect. OP3 is reject cylinder and IP5 is reject sensor. OP4 is the second conveyor.


As above this works but every so often the timings will be off causing it to reject when it shouldn't (potentially bit gone past/or bit hasn't been met)

 

[gclshortt]

http://www.plctalk.net/qanda/showthread.php?t=79956

Usually, when tracking parts on a conveyor, you would use bit shifting.
https://accautomation.ca/tag/plc-shift-register-example/

Regards,

 

[mrmennell]

http://www.plctalk.net/qanda/showthread.php?t=79956

Usually, when tracking parts on a conveyor, you would use bit shifting.
https://accautomation.ca/tag/plc-shift-register-example/

Regards,

Hi Garry,

Funny enough that article is where I derived using OP4 as my timing cycle I have T2 at 0.2 seconds which shifts the bit every 0.2 seconds (otherwise anything faster will make the shift register clear before my component gets to the end). R1/0 is my bit shift.

It works for the purpose of what it is, without being able to incorporate any further reliable components e.g. an encoded motor.

However I'm just wondering if there is a way to make this 100% system reliable. I get like 1 assembled product fail in like 50. And this is only through 1 test of it.

 

[gclshortt]

What I would do is extend the shift register to as many registers that are required at the timing rate that you want. This should give you a better resolution.
(Last bit would trigger the next register first bit.)

 

[mrmennell]

What I would do is extend the shift register to as many registers that are required at the timing rate that you want. This should give you a better resolution.
(Last bit would trigger the next register first bit.)

Would there be any other ways I could do this? I’m confident in this method and it works but I just wondered if there are any other ways?