ML1000 trying to compress program?

[504bloke]

B3/80 is short hand for B3:5/0.

See the attached for the changes Ken made plus the changes I recommended. Its up to 154 words of memory left now instead of 24 - more than enough to program several dozen more rungs.

RSLogix has a compare tool under Tools -> Compare that will compare this program with your original in side by side windows so you can easily find the changes and see the difference they make.

I also cleaned up the nested branches you had in the first three rungs of ladder 2. Extend branches, don't nest them. To extend a branch right click on the branch leg and select extend up or extend down, or if using the mnemonic editor type in NXB. Nesting branches adds more instructions and takes longer to process than extending branches.

I also changed the way non-retentive timers T4:1, T4:3, T4:5, T4:7, T4:9, T4:11, T4:13, T4:15, T4:17,T4:19 were reset, recovering 21 words.

I noticed you use a lot of JMP instructions. There is nothing wrong with the JMP instruction (I use it frequetly for looping) but I think some of your use of it could be avoided by structuring the program a little differently. Just say "no" to spaghetti code.


All in all though, pat yourself on the back.

Interesting thread, nice to see you chaps here helping someone out again

Alaric:

You learn something new every day !!

I didnt know Logix500 had nested branches !

Have never seen them or had the need to use them...

Nice to know you never stop learning

 

[timbo_uk]

Ken beat me to it.
In ladder 4, instead of brancing the Full_Reset_Pulse bit in with every single alarm, remove all the branches and program a seperate rung where the full reset pulse clears the entire word of alarms...
XIC Full_Reset_Pulse CLR B3:0 or if you don't want to clear the whole word, but just clear bits B3/0 though B3/10 with a bitwise AND
XIC Full_Reset_Pulse AND B3:0 -2048 B3:0
Either way will net you a gain of 6 words.

Sorry guys, I cannot get my head round this. Can anyone care to explain what goes on here please?

All the other suggestions and modifications I can follow.

I have gone through the modified code (and corrected a couple of the mistakes too (hey, you guys are only human too )

I have now seperated the two alarms for each print unit, so I can log them and indicate them seperately on the HMI.

I just need to add another reset signal for the next bank of fault flags (ie thats why I need to understand the Bitwise AND function)

Heres hoping I can get a reply before I go home today. Love to get this finished today.

Regards

Tim

 

[timbo_uk]

OK, I am replying to my own question, think I have worked it out.

Firstly -2048 in decimal is 1111100000000000 in binary (MSB on left)

So does the "Bitwise AND" work like this?

Look at bit 0 of source A (B3:0/0 = 1)
Look at bit 0 of source B (-2048 = 1111100000000000 = 0)

Then "AND" the 2 bits = 1 AND 0 = 0

Then put the result into Dest(ination) of B3:0.0 = 0

Then loop for ALL 16 bits? So the bits that in source B that are at zero will always set to zero; then the bits in source B that are set at 1 will always set to match existing?

I am pretty sure I am right on this one.

Lets see.......

 

[Lancie1]

Tried using this in my code, but it cannot work because of my structure (as mentioned earlier)

My timers that are used increment in 2, yet the integer addresses increment in 1's.

Yes, but Indexed Addressing would work for Ladder 8 MAX TIMES Rungs 11 through 21. There you have 11 Rungs with 11 Counters C5:0 to C5:10, and 11 Integer Addresses, N7:33 to N7:43. You could replace these with a loop with only 4 or 5 rungs using Indexed Addressing.

If you were willing to do a little Address Search-and Replace, you could change the N7 addresses in Rungs 0 to 10 to increment by 2. Then these 11 rungs could also be replaced with a loop with 4 or 5 Indexed address rungs, by adding 2 to S:24 on each loop iteration.

 

[Doug-P]

Referring to Ron Beaufort's post #2

I'm more familiar with the PLC-5 and SLC processors so, what follows may not apply - however:

In general, AB processors allocate memory for unused timer and counter addresses. That is, even though only T4:0, T4:2, T4:4, and T4:6 are used in the program, T4:1, T4:3, and T4:5 have been allocated. That's three words apiece. In addition to making file-type programming cleaner, sequential addressing would save a bit more memory - providing you delete from memory the now unused timers at the top of the file.

This next is getting a bit arcane but, I think you could save another one or two words by modifying Ron's loop in post #4. Instead of clearing S:24, load it with your max value and decrement through the file (change ADD S:24 1 S:24 to SUB S:24 1 S:24). Then, at the jump end of the loop, instead of comparing S:24 to zero, you could insert an XIO and check the processor 'Z' (zero) status flag, which will have just been conditioned by the preceding subtract instruction. This would also be marginally faster since you're just checking a bit and not comparing values. When S:24 goes to zero, the last operation will have been performed and the Z flag set. The XIO will now evaluate false and the JMP will not be taken thereby ending the loop.

Disclaimer: I didn't have an instruction set reference in front of me when I did this post.

 

[TConnolly]

OK, I am replying to my own question, think I have worked it out.

Firstly -2048 in decimal is 1111100000000000 in binary (MSB on left)

So does the "Bitwise AND" work like this?

Look at bit 0 of source A (B3:0/0 = 1)
Look at bit 0 of source B (-2048 = 1111100000000000 = 0)

Then "AND" the 2 bits = 1 AND 0 = 0

Then put the result into Dest(ination) of B3:0.0 = 0

Then loop for ALL 16 bits? So the bits that in source B that are at zero will always set to zero; then the bits in source B that are set at 1 will always set to match existing?

I am pretty sure I am right on this one.

Lets see.......

You got it, except it doesn't loop. The processor bitwise ANDs all 16 bits of the word simultaneously, like a single snapshot. Since the 11 least significant bits of source B are all 0, then the destination word will have all 11 of its least significant bits cleared. If any of the five most signifcant bits of Source A are set, then they will still be set in the destination.

 

[pandersen]

Extend branches, don't nest them.

I like to call badly nested rungs 'upside down cakes'. Everyone knows if a cake is upside down, it is probably heading towards the floor. You can't eat cake on the floor, and thats bad, therefore nested branches are bad.

 

[TConnolly]

Nice one.

And since it resembles an upside down wedding cake, its really really bad.

Of course ya'll know what they say about wedding cake anyways....