jseroka
Member
The Modicon compact 984 says:
Does anyone know the specifics of how the SRAM history/disable tables are set up? It says they start from the end of the SRAM and work forward.
We are using Proworx to program the PLC. And I think it is allowing us to have the 0x,1x,3x,4x registers overlap with the enable/history registers. And I am trying to determine where the conflict is.
Each 0x or 1x value implemented in user logic is represented by one bit in a word in
state RAM, by a bit in a word in the history table, and by a bit in a word in the
DISABLE table. In other words, for every discrete word in the state RAM table there
is one corresponding word in the history table and one corresponding word in the
DISABLE table.Counter input states for the previous scan are represented on page
F in an up-counter/down-counter history table. Each counter register is represented
by a single bit in a word in the table; a value of 1 indicates that the top input was ON
in the last scan, and a value of 0 indicates that the top input was OFF in the last scan.state RAM, by a bit in a word in the history table, and by a bit in a word in the
DISABLE table. In other words, for every discrete word in the state RAM table there
is one corresponding word in the history table and one corresponding word in the
DISABLE table.Counter input states for the previous scan are represented on page
F in an up-counter/down-counter history table. Each counter register is represented
by a single bit in a word in the table; a value of 1 indicates that the top input was ON
Does anyone know the specifics of how the SRAM history/disable tables are set up? It says they start from the end of the SRAM and work forward.
We are using Proworx to program the PLC. And I think it is allowing us to have the 0x,1x,3x,4x registers overlap with the enable/history registers. And I am trying to determine where the conflict is.