MVM vs AND speed. rs5000

[darkspark]

Hi All,



I know this is probably a strange question, but does anyone know what would be faster between a MVM and AND instruction?



I couldn't find a way to indirectly reference a single bit in a DINT. So I am using it to check if a bit is set in a DINT by creating a mask and checking if the result is greater than 0. Happy to hear of a better way if anyone knows one.


I am going for speed on this one so if you know any optimizations please let me know.

 

[lostcontrol]

Is there a reason you wouldn’t just use DINTTAG.Bit?
If you wanted to indirectly check the bit, you could also use DINTTAG.[BitIdx]

I am going for speed on this one so if you know any optimizations please let me know

Why are you so concerned ?

 

[darkspark]

I guess I didn't try square brackets. That is what I wanted to do originally.



It is just for playing around, I might do some tests to know what is fastest when I have some free time.



If you're wondering I am trying to do the PrimeSieve that DavePL has been doing on youtube. I don't do a lot of programming at work, so its a way to expand my skills.

 

[AustralIan]

https://literature.rockwellautomation.com/idc/groups/literature/documents/rm/logix-rm002_-en-p.pdf


AND is 0.014us, MVM is 0.134us, at least on some PLCs.


AND, the winner is.

 

[drbitboy]

https://literature.rockwellautomation.com/idc/groups/literature/documents/rm/logix-rm002_-en-p.pdf


AND is 0.014us, MVM is 0.134us, at least on some PLCs.


AND, the winner is.

Makes sense; they both do at least on AND, and MVM does more, although the factor of 9+ times slower is surprising: MVM ≡ (a AND mask) OR (a AND (NOT mask)); each of those OPs is 14μs or less each and there are only four of them, although extra memory is required; seems like it could be faster to do it like that.

Surprisingly, it's the opposite result on 1763s/RSLogix 500, although basically a tie: MVM is 13.18μs; AND is 13.24μs.

Not that it matters.

 

[Peter Nachtwey]

Measuring instruction times is difficult on modern PLCs/motion controllers because the new CPUs have a cache and use dynamic memory as opposed to static memory. The old CPUs like the 80186 didn't have a cache and were connected up directly to static memory. Any memory location could be accessed directly and the bus and instruction timing was predictable. The new CPUs read from memory in blocks of 4 to 16 words so even if you want only ONE word out of the block, the whole block must be read. Reading a block of memory is relatively slow. First the CPU must use at least 2 cycles to output the high and low address and activate the memory select. Then it must clock in the data using as many clocks as required for the size of data block. However, if the word you want is already in the cache then accessing the data usually takes just one cycle because it is access directly.
The CPU cache means that accessing code or data the first time will be slow but after that it can be very fast depending on whether the data is in the cache or not.

The fanatical code optimizers try to make sure that two commonly used sections of code or data do not end getting allocated to the same area in cache to avoid swapping out the cache. Modern CPUs have multiple layers of cache and sections of cache that avoid this problem.

So basically, trying to time an instruction is difficult and almost futile because it depends on so many things.

The AND instruction itself should be fast but if you count the time it takes to fetch to words, AND them together and then store the result then it can take much more time when implemented in a PLC Ladder block.