Omron WDT Eroor

[Girish]

Hi Ev1
I'm presently working on one of the old PlC by Omron
"SYSMAC CV–series CV500/CV1000 CVM1 CPU21". and I am a amateur in this field.

Now my main problem is the WDT ( Watch Dog Timer ) Error., Due to which
the entire systems goes into a reset condition & I'm unable to debug or in other words view any of the signals.
So I wanted to know what are the different conditions that causes this WDT error to go High.
And I also want to know if any timing violations cause this error if so what is the best
way to come out of this condition
& if anyone has worked on this board , can they please give me the list
of signals that are effecting the WDT.

There is a processor 80C186 being shared by TF250LF & TF 142NF, Can anyone
give me the detailed operation happening between them.

I'm very greatful for ur consideration.

Thanking You,

Grac Mascarenhas

 

[BobB]

I think you had better wait for Jay Anthony to log on for that one. Have never seen it before.
Other option is to contact your local Omron office or ring 1-800-556-6766.
Sounds like a processor problem or the program is taking too long to execute and causing the watch dog timer to time out.
beerchug

 

[Jay Anthony]

This was addressed at the following link:
WDT @ MrPLC.com

 

[Girish]

Hi ,

Heres the followup after Jay replied...
Hope this gives more info to other sas well who are trying to help me out ..
Here's the information

1.Yes the CPU is mounted on a rack(On CV500-BC101)

2.The Other modules present are a Digital Output module- OUT OD412

3.Only the Power & WDT , sometimes even this occurs ( WDT along with ALARM & ERROR LEDs Glow, but only for some time ,No idea why this happens )


4.only the S/W 4 is in the DOWN position

5.YES

6.NO

7.NO

8.CPU battery is OK

9.More about hardware:This is what I can give information about:

There are two chips (mainly )as I had told you earlier
TF250LF & TF 142NF and there is a processor 80C186 being shared by these, & there are some memory chips.There is a sequencing of operations done by the processor & the 2 chips try to get access according to some rule . Now I doubt there might be some timing violations while the two are trying to access the data from memory or some other data.
I need more information regarding the generation of the WDT, which is the module generating this and what the conditions are? :shrug:

Hope the information is sufficient. Can you also suggest me some study materials
regarding these which would be a great help.
Again thank you very much for your consideration.