rs-logix 5000

[RY_Guthrie]

I was wanting to program a timer in that would start timing when the the plc powered up, if i put a timer in a rung with no conditional contacts on the first pass will it start timing? and every time the plc is powered down will it reset and repeat the process when the plc comes back up? I am talking a ton timer not a re-tentative timer. Thanks for any help!

 

[widelto]

Use s:fs bit to start timer

 

[RY_Guthrie]

was wondering if 5000 had a first scan bit, thanks!

 

[Bering C Sparky]

Just curious,

If you put a first scan bit (XIC) as a conditional instruction in front of a timer.....

Would the timer actually keep timing after the first scan?

Or would it only time for 1 scan? (the first scan)

Seems that a first scan instruction would be just that.....only first scan.

Or am I thinking all wrong on this.

Just thinking out loud, but seems like you would need to latch the timer with at .TT bit in parallel with the FS bit to keep the timer, timing.


BCS

 

[widelto]

Just curious,

Just thinking out loud, but seems like you would need to latch the timer with at .TT bit in parallel with the FS bit to keep the timer, timing.


BCS

Or the enable bit .EN if desired. and the bit .DN in series to turn it off. If that´s the case.

 

[Bering C Sparky]

Or the enable bit .EN if desired.

Hi widelto,

So the first scan bit would only allow the one scan, as I thought then.

At first read of this thread I started thinking " I have been going at this first scan thing all wrong" since it seemed the below was being suggested.

***FS***
----] [----------------------------Timer


Had to check for my own benefit.

Thanks,
BCS

 

[widelto]

Bering you are correct.

 

[Bit_Bucket_07]

Just curious,

If you put a first scan bit (XIC) as a conditional instruction in front of a timer.....

Would the timer actually keep timing after the first scan?

Or would it only time for 1 scan? (the first scan)

Seems that a first scan instruction would be just that.....only first scan.

Or am I thinking all wrong on this.

Just thinking out loud, but seems like you would need to latch the timer with at .TT bit in parallel with the FS bit to keep the timer, timing.


BCS

Either use NOT the FS bit to enable the timer, or use the FS bit to Reset the timer while enabling it unconditionally.

 

[RY_Guthrie]

I used the first scan bit to initialize then used the .tt bits to latch timer on until it completed timing

 

[Doug-P]

This rung in Logix-500 does exactly what you want using the logic you described. Why would it not work on CLX?

 

[Bit_Bucket_07]

This rung in Logix-500 does exactly what you want using the logic you described. Why would it not work on CLX?

I think that it probably would. I've never tried it. My only concern is whether the accumulator register would be reset by cycling run mode. All outputs are reset to zero when the processor is stopped and restarted, aren't they?

 

[Doug-P]

All outputs are reset to zero when the processor is stopped and restarted, aren't they?

I cycled in and out of Run/Program a couple of times. The .acc value remains when going to program but clears and timing begins anew when going back to RUN

 

[ASF]

That's correct. Before a Logix PLC begins executing the code, it runs a pre-scan operation. During this prescan operation, all non-retentive timers are reset (ACC reset to zero, and .DN, .EN and .TT bits turned off).

So yes, just put a TON on a rung and it will reset and start timing every time your PLC goes to run mode, be that following a power up, a majjor fault, or a key switch from program to run.

 

[daba]

A Timer On (TON) instruction is "non-retentive".

That means that during the pre-scan it will be reset.

So if you had an unconditional rung driving a TON, it will get enabled and start timing on the first scan, and continue timing until the .ACC is greater than or equal to the .PRE.

Restarting the processor, either by going to run from program mode, or from a power-cycle, will trigger the "pre-scan" and a TON timer will be reset.

EDIT : ASF is a faster typist....

 

[JaxGTO]

All AB PLC's have a Per-Scan that scans all logic outputs as being false. The exception is for routines that do not have a hot branched JSR like a subroutine. Also latches will remain in the last state.

So your timer will be scanned false and thus reset in the Pre-Scan phase.