The bit field distribution (BTD) instruction

I have the following question when read a PLC book, regarding The bit field distribution (BTD) instruction. Thank you in advance for help.

Given:
Source address: N70:22
Source data: 0000000101101000
Source bit: 3
Destination address: N70:22 (same as source address)
Destination bit: 5
Length: 6

Question:
After the BTD instruction is executed, which of following is true?
A. Not allowed (error will occur during compilation) because the destination bit is within the source data location.
B. The result is that "101101" shifted left by two bits, i.e., 0000010110101000, leaving the lowest 2 bits of source data unchanged.
C. The process is to copy and write one bit at a time, starting from lowest bit, so that the bits 5 to 8 of the source data are changed during this process, and the result in N70:22 is 0000001010101000.

I would say the right answer is:
B. The result is that "101101" shifted left by two bits, i.e., 0000010110101000, leaving the lowest 2 bits of source data unchanged.

You can see my explanation on this link:
http://i66.tinypic.com/vnnp5d.jpg

Really appreciate your prompt help. May I ask if your answer is based on a real machine or simulator, or a convention? Is this a convention (or rule) that can apply to most PLCs or some particular PLC? Thank you again. (Please correct me if my question is not appropriate.)

I worked with BTD instruction on field, and it's work like I explained to you.
My answer is based on Allen Bradley literature, so it's rule.
I used BTD instruction only with Allen Bradley Compact Logix, but I am pretty sure in other PLC exist same logic for that instruction like in Allen Bradley.

Thank you again!!