Double Divide (DDV)

I am using RSLogix 500 and trying to figure out how the Double Divide function works. How does the 32 bit Math Register get it's initial value?

In MOST of the cases I have used the DDV instructions it has followed a MUL instruction where I was relatively confident that at some time the result would require a double integer. In the case of the MUL case the PLC loads the math registers (S:13 and S:14) with the results of the multiply as a normal part of operation. The DDV instruction assumes the math registers as it's 'Source A'. Status bit S:2/14 needs to be set to properly perform 32-bit math.

I have had situations where I have manually pre-loaded the math registers with the data I need. I had a situation where I needed to perform math on a double integer encoder count. This count came in to two successive integer locations. I just copied the contents of the integer registers into the math registers and then performed the double divide.

This second case is probably not as common as the 'double result of a MUL' case.

Keith