AB PLC5 Binary (Sub Sec.) Timing Word

Does anyone remember which status file word contains the binary timing bits? This word's individual bits toggle on and off with the rightmost LSB(Least Significant Bits) toggling fastest and decreasing in speed towards the left (MSB).

I'm looking for word which represents timebases less than seconds (Not S:23).

Can anyone suggest where I can find a listing of all the "S" file bits?

sorry the PLC-5 doesn't have the "free running clock" that the SLC and MicroLogix have ...

this thread might be helpful ...

I believe PLC5s don't have a free running clock that can be addressed like a SLC.

To get a list of status file address descriptions, you can create a new file in RSLogix5 and the S2 address database will be loaded with default descriptions. The database can then be exported to a .CSV file for use elsewhere.

I guess thats why I can't find it then.

You can create your own 50% dudy cycle 14 bit free running clock with a 0.01 timebase that is useful for up to 163.84 seconds

SOR BST TON T4:0 .01 32767 0 NXB OTU T4:0.ACC/14 BND EOR

Now access the individual bits of the accumulator as needed in the program, ie
T4:0.ACC/0 - toggles state every 0.01 seconds.
T4:0.ACC/2 - toggles state every 0.04 seconds.
T4:0.ACC/7 - toggles state every 1.28 seconds.
T4:0.ACC/12 - toggles state every 40.95 seconds.
T4:0.ACC/13 - toggles state every 81.92 seconds.

Bit 14 of the accumulator is always unconditionally reset. The lower 14 bits (0-13) continue to count as though nothing happened and the timer never times out. This preserves the timer accuracy. When using this method, never reset the timer.


If you need a longer time, then use

SOR BST TON T4:0 .01 32766 0 NXB XIC T4:0/DN RES T4:0 BND EOR

In this case we use 32766 as a preset because we need to end on an even number, ie bit T4:0.ACC/0 is clear because when we reset the timer that bit will be clear.

Note: programming a reset on a branch immediately below the timer will reset the timer immediately rather than waiting for the next scan to to perform the reset.
You could enter the rung as:
SOR XIO T4:0/DN TON T4:0 .01 32766 0 EOR
This will add anywhere from the scan time up to two times the scan time into your do it yourself free running clock every 327 seconds. The first method will add a value anywhere from 0.0 seconds up to the scan time to the free running clock every 327 seconds. You should evaluate your needs for maintaining accuracy.


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POP QUIZ:
Do you know why you can't unconditionally reset bit 15 instead of bit 14 in the first method above?
Why won't SOR BST TON T4:0 .01 32767 0 NXB OTU T4:0.ACC/15 BND EOR work?

.

Alaric said:

POP QUIZ:
Do you know why you can't unconditionally reset bit 15 instead of bit 14 in the first method above?
Why won't SOR BST TON T4:0 .01 32767 0 NXB OTU T4:0.ACC/15 BND EOR work?

Click to expand...

No, I tried it, is the bit reserved for ab use only? it just stays high and never resets. Is it a status of some sort?

Give me another that one was over my head

I would guess that you can't reset bit 15, because it's the "sign" bit.

Ken Moore said:

I would guess that you can't reset bit 15, because it's the "sign" bit.

Click to expand...

Ken,
What do you mean by "sign", the processor uses this as part of addressing?

see if this helps ...

sign bit basics

You can reset bit 15 all you want. But the reason the rung won't work is because a timer will never set bit 15. If bit 15 is set the number is negative. Unlike a counter, a timer will not wrap around, so when the timer ACC reaches the value of 32767, (01111111111111111 binary), it will simply stop counting.

On a related note, a quick and dirty test to see if a number is negative is to just test bit 15. This logic LES N7:0 0 OTE B3/0 and this logic XIC N7:0/15 OTE B3/0 do exactly the same thing, except the second one will execute faster.

Ron Beaufort said:

sign bit basics

Click to expand...

This helped alot, Thanks guys

Alaric,
Is it taken for granted that in the 2nd statement, that source "B" is "0", as is in the 1st statement?, or can you change it? (in the 2nd statement format?)

This is good stuff, thanks

When's the next quiz?

Yes, source B for the LES comparrison to check the sign of a number is 0.

In twos compliment 16 bit binary the only thing all negative numbers have in common is bit 15 is set. Likewise the only thing all positive numbers have in common is bit 15 is clear.** This sole commonality means we can test the sign of any number by looking at bit 15. If we were testing any other conditons (such as all numbers less than 5 as you inquired in your PM to me) then there is no such commonality and a comparrison instruction is the best choice.

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Continuing with twos complement numbers, do not think that you can change the sign of a number by just clearing or setting bit 15. (I assume you have looked at the link Ron provided.)

To illustrate this I will take just the case of the number -1 and 1.

1 is 0000000000000001
If I set bit fifteen then I would have 1000000000000001, which is
-32767.

-1 is 1111111111111111. If I clear bit 15 I will have 0111111111111111 which is 32767.

To change the sign you must multiply by -1 or use the NEG or ABS functions.

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To see twos compliment in action, try this exercise out:

• Open RSLogix500 and create a new SLC5/05 project.
• Close the ladder file view. You wont need it.
• Double click on the file N7 in the project tree to open the data file view. You should see just N7:0. Drag the data file window over to where it is not covering the project tree.
• Now doulbe click on the R6 file. In the lower left corner of the R6 file you will see R6 in a small field. Click the up arrow next to that to increment the file to N7.
• Now you should have two windows showing the N7 data file.
• Change the radix of one of the data file windows to binary.
• Now you can set and clear individual bits in the binary radix view, every time you press the enter key after changing a bit in the binary view, the decimal value will update in the decimal radix view. Try different bit combinations with both bit 15 set and clear and see what you get.

(** we can also test a nummer to see if it is even or odd by looking at bit 0. If N7:0/0 is clear, the number is even. If N7:0/0 is set, the number is odd. This commonality holds for all even and odd numbers. I am not aware of any other cases of commonality)

I don't know whether this will help but the timebase is still availabe, albeit by indirect means. The timer status and timebase live in a word which is called CTL (control) in a PLC-3. The timebase occupies the lower eight bits. I worked up this little program to watch the action of the timebase -

SOR XIO T4:0/DN TON T4:0 1.0 99 39 EOR
SOR COP #T4:0 #N12:0 3 EOR
SOR AND N12:0 0000000011111111 N12:3 EOR
SOR OTL B9/[N12:3] EOR

Create B9:15 and initialize its contents to zero, create also N12:3 or substitutes.

The COP copies the three timer words - CTL, PRE, ACC - to N12:0-2. The control word is now accessible as the contents of N12:0.

As the program runs, B9 will eventually fill with all 1s. It takes awhile I think because the timer and the program scan overlap each other.

YMMV