Omron Memory Map Help

Hi All,

New to Omron, looks straight forward (usually I do Siemens and AB) apart from one simple thing, for the life of me I cannot find any information regarding all their different memory areas. CI0, HR, AR, LR, DM, WR, EM, EM and Extended EM. Lots of help on the instructions etc but this basic information seems to have been overlooked.

CPU is a CJ1G-CPU45


Any Help – especially a link to a pdf would be most appreciated (already downloaded over 20 without result)


Thanks in advanced

PaperMan,

Download the W339 manual. There will be an entire section on the Memory Map. This should answer your questions.

Quick Answer:
CIO - Actual I/O point (unused can be internals)
HR - Holding Relay Area - maintains status thru power failure
AR - Auxillary Relay Area - mostly Status information
LR - Link Relay Area - used for PLC to PLC data xfer
DM (D) - Data Memory - Internal Data Storage Locations
WR (W) - Work Area - Internal Bits
EM - Extended Memory - Additional D type memory

Hope this will help.

Thanks

member.php?u=9328Spot on!

thanks alot gtsuport.

Paperman

Hello PaperMan,

Just to add to gt's help...
CIO (no need to prefix with CIO, just use the numbers) - Word and Bit addressable.
HR (prefix H) - Word and Bit addressable
AR (prefix A) - Word and Bit addressable (A0 - A447 Read Only)
LR - Not available for CS / CJ series
WR (prefix W) - Word and Bit addressable
DM (prefix D) - Word addressable only
EM (prefix E) - Word addressable only
On your CPU type, there are 3 banks of E (E0, E1, E3 - addressed as E3_100 for example)
Hope this helps.

Paulus said:

Hello PaperMan,

Just to add to gt's help...
CIO (no need to prefix with CIO, just use the numbers) - Word and Bit addressable.
HR (prefix H) - Word and Bit addressable.
AR (prefix A) - Word and Bit addressable (A0 - A447 Read Only)
LR - Not available for CS / CJ series
WR (prefix W) - Word and Bit addressable
DM (prefix D) - Word addressable. Bit addressable using instructions TST[350],TSTN[351],SETB[532] and RSETB[533].
EM (prefix E) - Word addressable. Bit addressable using instructions TST[350],TSTN[351],SETB[532] and RSETB[533].
On your CPU type, there are 3 banks of E (E0, E1, E3 - addressed as E3_100 for example)
Hope this helps.

Click to expand...

BITS N BYTES said:

Click to expand...

Hello BITS N BYTES,
Time for the gloves to come off...
OK, instructions can determine / set the status of D and E 'bits'.

What I meant however is, they are not freely addressable (i.e. LD D0.00 OUT E0_12.2) within a ladder program for example.

(Believe it or not, there is absolutely no reason why this should still be the case with the CS / CJ / CP range )

Hi Paulus,
I understand exactly what YOU meant.
BUT the original poster is a newbie to OMRON, I was simply clarifying that D and E memory can be accessed at both a WORD and BIT level.
Your statement "Word addressable only" could be misleading to those unfamiliar with OMRON.

Fair enough BITS N BYTES...
Sometimes do tend to imagine that everyone will know exactly what I mean!