So glad you corrected your original reply, Ron - I was halfway though correcting it for you when I noticed the edit.....
thanks ... good to know that someone has my back ... I'm working on putting together a little "dog and pony" show for Safety I/O in my "home" lab – and I don't multitask too well when I'm this tired ...
As for the ControlLogix, I do work on those too so could you explain the more complicated?
I may have to correct this in the morning – but here's the general idea ...
first let's start with an SLC or MicroLogix system ...
suppose that you're using a LATCH (OTL) instruction – and an UNLATCH (OTU) instruction – and that both rungs are FALSE ...
suppose that the bit/box has a status of ONE when you shut down the system ...
when the system powers back up again (go to run) the bit/box should still have a ONE status ... it "retains" its status is how this operation is usually described ...
but suppose that you add another rung – even an UNconditional rung – with an OTE instruction for the same bit address – and that you place this rung in an UNUSED subroutine ... specifically, the subroutine has NO way to be executed ... no JSR – no STI – no DII – no "NUTHIN" to tell the processor to scan/execute the OTE rung ...
(some programmers create a "scrap pile" subroutine – and "park" unused rungs in it – just in case they might need them later) ...
now when you power down – and back up – or go to program mode and then back to run mode (go to run) – the LATCH bit will NOT retain its ON status ... specifically, PRE-SCAN will find that "UNUSED" (orphan) OTE instruction – and go write a ZERO into the bit/box ... in other words, the LATCHED bit "won't hold" its ONE status ...
now for a ControlLogix or CompactLogix system ...
suppose that we set up the same test as before ...
now when you power down – and back up – or go to program mode and then back to run mode (go to run) – the LATCH bit WILL retain its ON status ... specifically, PRE-SCAN operation will NOT find and execute that "UNUSED" subroutine ... in this case, the LATCHED bit "will hold" its ONE status (at go to run) ...
that's the basic difference that I was referring to earlier ...
now add a JSR rung to "call" the unused subroutines in each of the systems – and make both of the JSR rungs FALSE ... for example: use an AFI instruction for the Control/CompactLogix JSR rung – and maybe use just an XIC left in a ZERO status for the SLC/MicroLogix JSR rung ...
if my memory serves correctly – the LATCHED bit/box in the Control/CompactLogix system will now be reset to OFF – just like the SLC/MicroLogix ...
basic idea (again from memory) the Control/CompactLogix platform must have some "WAY" – some "PATH" – in order to find and scan the unused subroutine on PRE-SCAN – EVEN IF THAT PATH IS GUARANTEED TO BE FALSE ... the SLC/MicroLogix platform doesn't need any sort of path ... PRE-SCAN will go find that orphaned OTE instruction regardless ...
DISCLAIMER: I'm doing this by memory – and don't have time to double-check it – but I'd bet more than pocket change that I've got it right ...
closing out – this type of thing is one reason why I personally don't refer to "seal-in" rung constructions as "latched" rungs ... many people do that – but there is a BIG difference between how actual LATCHED/UNLATCHED rungs operate – and how "SEALED-IN" rungs operate ...