Peter Nachtwey said:
...To get that info you would need to see the design and I doubt Rockwell will share that info.
Peter,
The specs for these CPUs are in the link I gave above, and no, they are not readily available from Rockwell.
I'll post them here again...
CompactLogix controllers, run on Freescale MCP855T PowerPC microprocessors, namely PowerQUICC.
Their package type is PBGA 357.
They use 32 Bit Power Architecture and feature 50MHz, SoC, CPM, ENET, ATM, HDLC, PCMCIA.
They are the baby of the MCP860 PowerPC family.
Features...
Embedded MPC8xx core with
105 MIPS at 80 MHz (using Dhrystone 2.1)
4-Kbyte Instruction Cache
4-Kbyte Data Cache
8 Kb Dual Port RAM
Instruction and Data MMUs
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)
32 Address Lines
Complete Static Design (0-80 MHz Operation)
Memory Controller (Eight Banks)
General-Purpose Timers
System Integration Unit (SIU)
Interrupts
Communications Processor Module (RISC CPM)
Four Baud Rate Generators
One SCC (Serial Communication Controller)
Two SMCs (Serial Management Channels)
One SPI (Serial Peripheral Interface)
One I2C (Inter-Integrated Circuit) Port
Time-Slot Assigner
Parallel Interface Port
PCMCIA Interface
Low Power Support
Debug Interface
3.3 V Operation with 3.3V I/O
...
Older ControlLogix up to L6x run on Philips Semiconductor (now NXP) Atlas ARM 32-bit RISC VY22575 microprocessors.
Features...
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.
63 MIPS @ 70 MHz (using Dhrystone 2.1) maximum CPU clock available from programmable on-chip PLL with a possible input frequency of 10 MHz to 25 MHz and a settling time of 100 ms.
128-bit wide interface/accelerator enables high-speed 70 MHz operation.
On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz.
2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip Bash program memory.
ISP/IAP via on-chip bootloader software.
Single Bash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms.
EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.
The 10-bit A/D converter provides eight analog inputs, with conversion times as low as 2.44 ms per channel and dedicated result registers to minimize interrupt overhead.
Two 32-bit timers/external event counters with combined seven capture and seven compare channels.
Two 16-bit timers/external event counters with combined three capture and seven compare channels.
Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input.
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.
Vectored interrupt controller with configurable priorities and vector addresses.
Up to thirty-two 5 V tolerant fast general purpose I/O pins.
Up to 13 edge or level sensitive external interrupt pins available.
Power saving modes include Idle mode, Power-down mode with RTC active, and Power-down mode.
Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization.
Processor wake-up from Power-down mode via external interrupt or RTC.
...
Peter Nachtwey said:
...Memory wait states can be a killer and really slow down the CPU...You may get a relative speed like 1.2 to 1.
As ARM processors are quite common in the PLC world, this is quite relevant...
Dhrystone and MIPs (Million Instructions Per Sec) performance of ARM processors
The MIPS figures which ARM (and most of the industry) quotes are "Dhrystone VAX MIPs". The idea behind this measure is to compare the performance of a machine against the performance of a reference machine. The industry adopted the VAX 11/780 as the reference 1 MIP machine.
The benchmark is calculated by measuring the number of Dhrystones per second for the system, and then dividing that figure by the number of Dhrystones per second achieved by the reference machine.
So "80 MIPS" means "80 Dhrystone VAX MIPS", which means 80 times faster than a VAX 11/780. The reason for comparing against a reference machine is that it avoids the need to argue about differences in instruction sets.
RISC processors tend to have lots of simple instructions. CISC machines like x86 and VAX tend to have fewer, more complex instructions. If you just counted the number of instructions per second of a machine directly, then machines with simple instructions would get higher instructions-per-second results, even though it would not be telling you whether it gets the job done any faster.
By comparing how fast a machine gets a given piece of work done against how fast other machines get that piece of work done, the question of the different instruction sets is avoided.
There are two different versions of the Dhrystone benchmark commonly quoted:
Dhrystone 1.1
Dhrystone 2.1
ARM quotes Dhrystone 2.1 figures. The VAX 11/780 achieves 1757 Dhrystones per second.
- The maximum performance of the ARM7 family is 0.9 Dhrystone VAX MIPS per MHz.
- The maximum performance of the ARM9 family is 1.1 Dhrystone VAX MIPS per MHz.
These figures assume ARM code running from 32-bit wide, zero wait-state memory. If there are wait-states, or (for cores with caches) the caches are disabled, then the performance figures will be lower.
To estimate how many ARM instructions are executed per second then simply divide the frequency by the average CPI (Cycles Per Instruction) for the core.
- The average CPI for the ARM7 family is about 1.9 cycles per instruction.
- The average CPI for the ARM9 family is about 1.5 cycles per instruction.
Regards,
George