Is there a way to reverse the logic of a rung in RSLogix

[Iner]

Hi



I did not find the instruction. I am a very part time user of Rockwell soft.


I am looking for the same "NOT" function that you can use in Schneider and Siemens software.



When you have a lot of parallel bits that you want to sum it's much more readable to write them with a NOT than putting them in parallel.



Like this exemple in Schneider's soft.

 

[ecad575]

There is a NOT-function under Move/Logical.

Alternatively can't you just invert all the inputs by changing from XIC to XIO?

I don't know Schneider so sorry if misunderstood.

 

[drbitboy]

https://www.plctalk.net/qanda/showthread.php?t=89109


Summary



There is NOT in ST and BNOT in FB (Logix 5000).




TL;DR


In ladder, other than the PLC/5 INV instruction, just the obvious, trivial solution:

    A      B    ...  notSortie
---]/[----]/[---...----( )---

   notSortie     Sortie
-----]/[----------( )----

Which is at least as readable as the Scheider and Siemens solution (similar, perhaps less, use of vertical real estate).


If the inverted boolean was written to an intermediate bit of an integer, there could be silly solution with an XOR to keep it in one rung (although the solution above could be written as one rung):

       A   ...    I/0                             I/0   Sortie
--+---]/[--...----( )-----+---[XOR            ]---] [----( )---
  |                       |   [SourceA integer]
  |     I/0               |   [SourceB   0001h]
  +-----]/[---------------+   [Dest    integer]

 

[Holmux]

In Logix, you would use a DINT and address the bits

Here is an example where I used a DINT = Test

Then compare the DINT to 0 using a NEQ command

 

[daba]

In Logix, you would use a DINT and address the bits

Here is an example where I used a DINT = Test

Then compare the DINT to 0 using a NEQ command

What if you can't use DINT bits ? Why not do what has been suggested and just follow the inverted logic with another rung that inverts it back to normal.

The vertical ladder "OR" functionality gets cumbersome when lots of bits are used, so I very often make a "NOR" rung, then invert the output of that on the next rung.

 

[Iner]

Thanks for the replies.


I think that creating the intermediate bit is the simpliest. Using a DINT is possible, but it takes mores space and even if it's a member of a DINT, you may not want to evaluate all the members of that DINT.


It's curious that Rockwell have choosen to not include this very basic instruction in their software.


Have they thought that people would have trouble with reverse logic?

 

[daba]

Thanks for the replies.


I think that creating the intermediate bit is the simpliest. Using a DINT is possible, but it takes mores space and even if it's a member of a DINT, you may not want to evaluate all the members of that DINT.


It's curious that Rockwell have choosen to not include this very basic instruction in their software.


Have they thought that people would have trouble with reverse logic?

Add-On Instruction ?

EDIT : Scrub that idea... it is way more complex than just inverting the bit on the next rung. Having said that, I would most likely do it on the same rung (with the inversion on a branch), so that you cannot get the two rungs separated, or even moved !

I believe the reason it was not included in any A-B instruction set, and I'm sure it was considered, is that the rule is once a rung or branch has been "falsified", you cannot turn it "true" again. This keeps everything conformal and easily understood by everyone.

 

[RockyLeafs]

AOI (add on instruction) is a good idea if you really do miss the NOT feature in the other PLC.
Only thing I dont like about AOI is that you have to assign them a tag.

I remember some PLCs (Beckhoff TwinCAT I remember for sure) you could create simple functions and not have a tag assigned to just the function. But at this point I guess I'm just picky.

 

[daba]

AOI (add on instruction) is a good idea if you really do miss the NOT feature in the other PLC.
Only thing I dont like about AOI is that you have to assign them a tag.

I remember some PLCs (Beckhoff TwinCAT I remember for sure) you could create simple functions and not have a tag assigned to just the function. But at this point I guess I'm just picky.

Forget the AOI solution, it won't work, because the AOI logic cannot write to the .EnableOut, which is what you want it to do to use the AOI "in-line" with the following instructions. It was a dumb idea anyway, because you would need additional logic in an "Enable-In-False" routine, to to the opposite of when the Enable-In is true.}

Intermediate bit is the way to go, and if I had lots of instances of large OR gates, I would probably just keep re-using the one intermediate tag to save memory, call it "logic_extend" or the like, and suffer the "Duplicate Destructive Bit" warnings in the verification.

However, memory is cheap these days, so XIO We_Have_No_Plan, OTE We_Have_A_Plan speaks volumes ...

 

[Mike Nash]

Just a thought. "Seems" to work in simulator.

[FONT="Lucida Console"]
Faulted    F1     F2     F3     F4     Faulted
--(L)------]/[----]/[----]/[----]/[------(U)---
[/FONT]

 

[drbitboy]

Just a thought. "Seems" to work in simulator.

[FONT=Lucida Console]
Faulted    F1     F2     F3     F4     Faulted
--(L)------]/[----]/[----]/[----]/[------(U)---
[/FONT]

oh man, that is su-weet!

 

[daba]

Just a thought. "Seems" to work in simulator.

[FONT=Lucida Console]
Faulted    F1     F2     F3     F4     Faulted
--(L)------]/[----]/[----]/[----]/[------(U)---
[/FONT]

What if the tag "Faulted" is read by comms from somewhere else, or read in a periodic or event task ?


Needs to be bracketed with UID and UIE rungs to be 100%

 

[Iner]

Just a thought. "Seems" to work in simulator.

[FONT=Lucida Console]
Faulted    F1     F2     F3     F4     Faulted
--(L)------]/[----]/[----]/[----]/[------(U)---
[/FONT]

Wow, would not have thought about that, very creative !

 

[cidchase]

I can find no "Fault" in that logic.

 

[daba]

I can find no Fault in that logic.

Except that it'll only be allowed on Logix5000, no other A-B platform supports outputs at the head of the rung.


EDIT : Of course the same logic could be re-structured to make it more compatible with other platforms ...