Logic Verification for Ladder Diagrams

teddi

Member
Join Date
Oct 2008
Location
Vancouver
Posts
2
I have to do a project on verification of ladder diagram.
Its supposed to be a binary logic verification.

I am supposed to come up with some test cases that prove the logic on a ladder diagram could be in a conflict.

Example (assuming that all inputs and outputs are binary)
-------

CASE 1
------
- the most obvious and simple one

x ^ ~x -> y


CASE 2
------
- 2 same inputs giving opposite results
- or 2 completely opposite inputs to give same output

x ^ y -> z
x ^ y -> ~z

OR

x ^ y -> z
~x ^ ~y -> z


CASE 3
------

a -> b
~b -> a

OR

~a -> b
b -> a



CASE 4
------
- indirect conflict
(since x is a subset of b it cannot be used in conjunction with a ~b)

b ^ ~y -> x
~b ^ x -> w



Has anyone done something similar on these lines.
If there are more test cases that I have missed out.
And if these test cases are correct?

Thanks again.

-teddi
 

Similar Topics

I need some advice people on a small modification I need to do to a process. I have a contrologix PLC running this process. I'm currently using a...
Replies
2
Views
1,443
I got my PanelView Plus 7 working with a Micrologix 1500. How would I connect my laptop to the PanelView to view the ladder logic while operating...
Replies
6
Views
115
Hello, I am trying to replicate a piece of logic on the PLC5 onto an SEL RTAC. I am using ladder on SEL and FBD. I am having issue on the ladder...
Replies
13
Views
228
Hello again..trying something on an existing poorly written program and just wanted to double check something system is an A-B MicroLogix 1200 In...
Replies
5
Views
169
Good morning fellow sea captains and wizards, I am being asked to do the above and obtain 4 values from each slave, I know about the MRX and MWX...
Replies
32
Views
833
Back
Top Bottom