The thing you'll need to watch out for most are computations and block moves. For example, a block move in the network at r5,c2 will execute before an emath instruction at r2,c5, even though the emath instruction is at the top of the network. The execution order is essential because the block move is needed to set up the data in the registers for the emath instruction so it must execute first. Also keep in mind that even though an output instruction may appear in the right hand column, it's true solve column might be any column to the left, therefore an output at r7,c2 will solve before anything to the right and above of it, even though it appears to be in the lower right corner of the network. Depending on your logic this may or may not matter. To avoid any confusion over the actual sovle column, set your Proworx or Concept software to display the coils in the true solve column while you are translating the program. Be aware that power can flow up from bottom to top in a Modicon network. You may wonder how the processor handles certain functions, its helpful to know that a Modicon 984 remembers the state of everything from the previous scan while it solves the current scan, and then updates the previous scan image after the current scan has completed. Converting Modicon to AB is not difficult as long as you understand the scan differences.
Do you have a reference on the 984 instruction set? If you are using Proworx NXT or Proworx 32 then the online instruction help is the best reference there is, its better than the manuals. If you are working from a print out or some of the older software then you can download the logic block library manuals at
http://forums.mrplc.com/index.php?autocom=downloads&showcat=25. The reference manual PDF files are way too big to post.
Proworx32 is buggy by the way - I think is suffers from ADD, if it appears to hang just wait a minute, eventually it will remember it is supposed to be doing something.
In the Modicon 984 the networks are divided by the user into sections and each section is scheduled for scanning. Its possible to schedule a section more than once per scan. There are no separate subroutines like you are used to in AB processors. Instead a section of code is left unscheduled and can then be treated as a subroutine with a subroutine call and return even though it will appear as part of one long monolithic program.