Your point about improving the overall scan time is correct, but your test doesn't necessarily prove your theory.
Again, I've only seen this specifically in relation to the Logix 5000 platform, but if you run the same test on a CLX, you'll get the same results, because the instructions take different times to execute depending on the rung-in condition.
On something like a TON, the difference is not enormous, because it has a number of tasks to do in either case. Changing the state of .EN, .DN, .TT bits, adjusting .ACC registers, etc. But on an XIO or XIC, it's a more clear-cut case of:
Rung-In True: Check state of tag, set rung-out condition based on state of tag and instruction type
Rung-In False: set rung-out false
It doesn't actually have to perform any logic if the rung-in condition is false, so it's much faster to execute. Same with a MOV or a COP or a GRT or a LES or any number of other things.
There's actually a document somewhere on the KB that gives the approximate execution time of each instruction, separated by rung-in condition true and rung-in condition false. It's probably wildly out of date by now, but the long and short of it is, most (or possible all) instructions execute faster if the rung-in condition is false. So, as to your point about scan time - yes, you'll still get
faster execution of a given rung if you put the most likely false conditions at the start of the rung, but each instruction on the rung is still being executed. It's just that if your rung goes "false" early on, the remaining instructions take much less time to execute.
Again, can't 100% promise that it's the case for an SLC, but I don't believe that the test you ran proves me wrong. If you wanted to prove me wrong (and I'm happy to be proved wrong, because then I've learned something!), you'd run three tests:
1. 1000 rungs with 10 XIC's on each, followed by an OTE. All XIC's except the last one on each rung are true
2. 1000 rungs with 10 XIC's on each, followed by an OTE. First XIC on each rung is false
3. 1000 rungs with a single, true XIC and a single OTE on each
If I'm right, Test 1 will be fastest, followed by Test 2, followed by Test 3. If you're right, Test 1 will be fastest and Tests 2 & 3 will be identical.
I don't have an SLC handy to test with, but maybe I'll set up my Compact Logix later on and at least prove my theory on that platform