Lukasz_Poland
Member
Hello
I have got a problem with positive edge from "system clock memory byte" in Tia Portal. I would like to change byte"system clock memory" to another byte but it should be "positive edge byte"
I saw that function with XOW and AW but it was in STL language and I dont know how to write it in SCL.
Sorry for my poor English.
I have got a problem with positive edge from "system clock memory byte" in Tia Portal. I would like to change byte"system clock memory" to another byte but it should be "positive edge byte"
I saw that function with XOW and AW but it was in STL language and I dont know how to write it in SCL.
Sorry for my poor English.