Having trouble setting up a register.

Join Date
May 2016
Location
Holland, Michigan
Posts
2
Hello all,

I'm a student in an advanced level PLC programming class. A project that I'm working on moves boxes through a sorting station and onto one of three lines. Photo-eyes monitor the status of a line; if a line is low on boxes, the sorting station adjusts so the infeed conveyor pushes a group of 6 onto that line. The sorting station consists of two solenoids attached to two "flappers" - similar to a pinball machine. I should also mention that I have control over when to release the infeed conveyor, and that it releases in groups of 6.

My problem is setting up the flappers to do "first come, first served". Multiple lines could be low at once, so I need to do make sure they're handled appropriately.

I know that a register is the way to go for this, but I'm not sure how to implement it. Here's how I envision it:

-3 lines means the register needs to only be 3 bits big
-When line 1 is empty and needs to be filled, put a "1" in B3:4/1 (B3 is the hypothetical register).
-When line 2 is empty and needs to be filled, put a "1" in B3:4/2.
-When line 3 is empty and needs to be filled, put a "1" in B3:4/3.

If any of the lines are full (IE the photoeye is blocked), put a 0 into the lines respective slot.

I was thinking of having a counter sort through the register (IE B3:4/[C5:0.ACC]). If it finds a 1, fill that line. If it finds a 0, move on. Is this the best implementation though? I think what I'm getting caught up on is how to cycle through the register. Because the lines empty at random, there's no good way to do it that my inexperienced mind can think of.

The software I'm using is RSLogix5000. If anyone could point anything out to me, I'd be eternally grateful.
 
jstolaruk,

you are on the right track, but this is what I would do.

your flags are in place, if any of those 3 are "1" use bit 4 to set a flag.
this flag starts the box feed system and resets when the lane is full.

it also will tell the remainder of your code to keep track of which lane needs boxes next.

think of it for a while,

james
 
It sounds to me like this exercise is geared toward using a FIFO (First In First Out) register. First line to say "empty" is the first line to get boxes.

As jstolaruk mentioned, you'll need to confirm whether you're using RSLogix 500 or 5000 to get accurate advice, but my tip to get you started would be to look at the FFL and FFU instructions, and rather than setting a discrete bit to specify a lane being empty, use integers in a FIFO queue to numerically indicate which lane was empty and in what order.
 
I was thinking of having a counter sort through the register (IE B3:4/[C5:0.ACC]). If it finds a 1, fill that line. If it finds a 0, move on. Is this the best implementation though? I think what I'm getting caught up on is how to cycle through the register. Because the lines empty at random, there's no good way to do it that my inexperienced mind can think of.

Your approach (indirect addressing the B3:4 bits) will work but would be made easier by substituting an integer - read N7:x - register for the counter. When N7:x = 1, test line one. If full, move a two to N7:x. Else release work into line one. When done, move a two to N7:x. When N7:x = 2, test line two. Same for line three. When three done, load the starting value to N7:x.

See state machine - https://en.wikipedia.org/wiki/Finite-state_machine
 
Welcome to the forum!
Are you sure you're using RSLogix 5000 and not RSLogix 500? The register locations don't jive.

Thank you for the welcome! I can tell this is a very thoughtful and thorough community. Makes me excited to be a part of it. You are correct; I hit one too many 0's. I am indeed using RSLogix 500. Tricky.

jstolaruk,

you are on the right track, but this is what I would do.

your flags are in place, if any of those 3 are "1" use bit 4 to set a flag.
this flag starts the box feed system and resets when the lane is full.

it also will tell the remainder of your code to keep track of which lane needs boxes next.

think of it for a while,

james

Thank you for your insight James. I really like the idea of using a 4th bit as a "flag". I will definitely take note of this and see if I can make it work; I already have some idea of how to implement it. I appreciate it.

It sounds to me like this exercise is geared toward using a FIFO (First In First Out) register. First line to say "empty" is the first line to get boxes.

As jstolaruk mentioned, you'll need to confirm whether you're using RSLogix 500 or 5000 to get accurate advice, but my tip to get you started would be to look at the FFL and FFU instructions, and rather than setting a discrete bit to specify a lane being empty, use integers in a FIFO queue to numerically indicate which lane was empty and in what order.

Yeah, you're right. I think it's a great project for learning registers with. I'm using RSLogix 500, not 5000. Setting up the FFL or FFU is a bit complicated for me right now, but I can see what you're getting at. I will keep reading it and see what I can come up. Thank you for your input.

Your approach (indirect addressing the B3:4 bits) will work but would be made easier by substituting an integer - read N7:x - register for the counter. When N7:x = 1, test line one. If full, move a two to N7:x. Else release work into line one. When done, move a two to N7:x. When N7:x = 2, test line two. Same for line three. When three done, load the starting value to N7:x.

See state machine - https://en.wikipedia.org/wiki/Finite-state_machine

Oh, now that's interesting. It gives me more control than the counter as well as more flexibility. This is the closest to what I had already come up with so I think I'll try this first. The others solutions seem more robust, though. But I really like your idea of using an integer instead. Definitely something to take note of and file away for future use. I really appreciate it Doug! And thank you for the link; I'll read through it on my lunch break. Cheers!
 

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