Ken Roach said:I did a routine a few weeks ago that put the SLC into 32-bit mode for just one scan, so that my user could perform one 32-bit Subtract and not have to modify the rest of his existing program. I can dig that out if you like.
N7:1 N7:0
+ N7:3 N7:2
---------
N7:5 N7:6
Basically I did it like this:
CLR N7:9 THIS IS WHERE THE CARRY WILL BE STORED
ADD N7:0 N7:2 N7:4 ADD THE LOW WORDS
XIC S:0/0 MOV 1 N7:9 STORE A ONE IF THERE IS A CARRY
OTU S5:0 UNLATCH THE OVERFLOW TRAP
ADD N7:1 N7:3 N7:5 ADD THE HIGH WORDS
ADD N7:9 N7:5 N7:5 ADD THE CARRY
32-Bit Addition
If you are using a Series C or later 5/02, or a 5/03, 5/04, 5/05 or MicroLogix processor (capable of 32-bit addition and subtraction), you can set the math overflow bit (S:2/14) in the status file. This causes the unsigned, truncated, least significant 16 bits to remain in the destination.
If this bit is not set and an underflow or overflow conditions occurs, the operation will be the same as with a Series B 5/02 processor. The destination address will contain a 32767 (if the result is positive) or -32768 (if the result is negative).
© Rockwell Software 2000
OTL S:2/14 DISABLE OVERFLOW LIMITING
CLR N7:9 THIS IS WHERE THE CARRY WILL BE STORED
ADD N7:0 N7:2 N7:4 ADD THE LOW WORDS
XIC S:0/0 MOV 1 N7:9 STORE A ONE IF THERE IS A CARRY
OTU S5:0 UNLATCH THE OVERFLOW TRAP
ADD N7:1 N7:3 N7:5 ADD THE HIGH WORDS
ADD N7:9 N7:5 N7:5 ADD THE CARRY
OTU S:2/14 ENABLE OVERFLOW LIMITING
Scan Toggle Bit S:33/9
This bit changes state each and every execution of an END, TND, or REF instruction. It is always cleared when entering RUN mode. Use this bit in your user program for applications such as multiplexing subroutine execution.
RSLogix 500 - Copyright Rockwell Software 2000, 2001m
B3/2 B3/2
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