Help with Converting STL to SCL

Olledvin · Oct 2, 2023

Hi!

I am working on a project were we will be replacing an 300 CPU with a 1500 CPU and we are working on migrating / converting code. There is a integral block used to handle analog signals, write/read to Cont_C regulator as well as read/write to WinCC with Static variables and OS messages.

I have removed segments of the code that was related to OS messages, we will be instead using Program Alarms. It would be GREATLY appreciated if we could get some help with converting the STL code to something easily understandable (not used to STL I guess, always worked in SCL + FDB).

The code is the following:

SET
SAVE
= L 40.1
A #AUT_EXT_PULSM_P
NOT
A #AUT_EXT
= #AUT_EXT_PULS_P
A #AUT_EXT
= #AUT_EXT_PULSM_P
A #AUT_EXT_PULS_P
JCN A7d0
SET
= #MAN_AUTO
A7d0: L #DB_CONT_C
T LW 42
CLR
A #MAN_AUTO
NOT
O #TRK_ON
OPN DB [LW 42]
= DBX 0.1
A #MAN_AUTO
= #QAUTO
NOT
= #QMAN
A #TRK_ON
A #MAN_AUTO
= #QTRK
A #TRK_ON
A #MAN_AUTO
JCN A7d1
T LW 42
L #TRK_VAL
OPN DB [LW 42]
T DBD 16
JU A7d2
A7d1: L #DB_CONT_C
T LW 42
L #MAN_VAL
OPN DB [LW 42]
T DBD 16
A7d2: CLR
A #SP_INT_EXT
JCN A7d3
L #SP_EXT
T #SP_TEMP
JU A7d4
A7d3: L #SP_INT
T #SP_TEMP
A7d4: L #SP_TEMP
L #SP_HLM
>R
JCN A7d5
T #SP_TEMP
T #SP_INT
JU A7d7
A7d5: L #SP_TEMP
L #SP_LLM
<R
JCN A7d7
T #SP_TEMP
T #SP_INT
A7d7: CLR
A #SP_INT_EXT
JCN A7d8
L #SP_TEMP
T #SP_INT
A7d8: L #DB_CONT_C
T LW 42
L #SP_TEMP
OPN DB [LW 42]
T DBD 6
TAK
T LW 42
OPN DB [LW 42]
L DBD 6
T #SP_AKT
L #SP_EXT
T #SP_EXT_OP
L #SP_HLM
T #SP_HLM_OP
L #SP_LLM
T #SP_LLM_OP
L #DB_CONT_C
T LW 42
OPN DB [LW 42]
L DBD 92
T #PV
L #PV_HLM
T #PV_HLM_OP
L #PV_LLM
T #PV_LLM_OP
L #DB_CONT_C
T LW 42
OPN DB [LW 42]
L DBD 72
T #LMN
TAK
T LW 42
L #LMN_HLM
OPN DB [LW 42]
T DBD 40
TAK
T LW 42
L #LMN_LLM
OPN DB [LW 42]
T DBD 44
L #LMN_HLM
T #LMN_HLM_OP
TAK
T #LMN_LLM_OP
L #PVH_ALM
L #PVH_ALM_TEMP
<>R
JCN A7d9
L #PVH_ALM
T #PVH_ALM_TEMP
T #PVH_ALM_OP
A7d9: L #PVH_ALM_OP
L #PVH_ALM_TEMP
<>R
JCN A7da
L #PVH_ALM_OP
T #PVH_ALM_TEMP
T #PVH_ALM
A7da: L #PVL_ALM
L #PVL_ALM_TEMP
<>R
JCN A7db
L #PVL_ALM
T #PVL_ALM_TEMP
T #PVL_ALM_OP
A7db: L #PVL_ALM_OP
L #PVL_ALM_TEMP
<>R
JCN A7dc
L #PVL_ALM_OP
T #PVL_ALM_TEMP
T #PVL_ALM
A7dc: L #PVH_WRN
L #PVH_WRN_TEMP
<>R
JCN A7dd
L #PVH_WRN
T #PVH_WRN_TEMP
T #PVH_WRN_OP
A7dd: L #PVH_WRN_OP
L #PVH_WRN_TEMP
<>R
JCN A7de
L #PVH_WRN_OP
T #PVH_WRN_TEMP
T #PVH_WRN
A7de: L #PVL_WRN
L #PVL_WRN_TEMP
<>R
JCN A7df
L #PVL_WRN
T #PVL_WRN_TEMP
T #PVL_WRN_OP
A7df: L #PVL_WRN_OP
L #PVL_WRN_TEMP
<>R
JCN A7e0
L #PVL_WRN_OP
T #PVL_WRN_TEMP
T #PVL_WRN
A7e0: L #HYSTERES
L #HYST_TEMP
<>R
JCN A7e1
L #HYSTERES
T #HYST_TEMP
T #HYST_OP
A7e1: L #HYST_OP
L #HYST_TEMP
<>R
JCN A7e2
L #HYST_OP
T #HYST_TEMP
T #HYSTERES
A7e2: L #GAIN
L #GAIN_TEMP
<>R
JCN A7e3
L #GAIN
T #GAIN_TEMP
T #GAIN_OP
A7e3: L #GAIN_OP
L #GAIN_TEMP
<>R
JCN A7e4
L #GAIN_OP
T #GAIN_TEMP
T #GAIN
A7e4: L #DB_CONT_C
T LW 42
L #GAIN
OPN DB [LW 42]
T DBD 20
L #I_TID
L #I_TID_TEMP
<>D
JCN A7e5
L #I_TID
T #I_TID_TEMP
L L#1000
/D
T #I_TID_OP
A7e5: L #I_TID_OP
L L#1000
*D
T #I_TID_1000
L #I_TID_TEMP
<>D
JCN A7e6
L #I_TID_1000
T #I_TID_TEMP
T #I_TID
A7e6: L #DB_CONT_C
T LW 42
L #I_TID
OPN DB [LW 42]
T DBD 24
L #D_TID
L #D_TID_TEMP
<>D
JCN A7e7
L #D_TID
T #D_TID_TEMP
L L#1000
/D
T #D_TID_OP
A7e7: L #D_TID_OP
L L#1000
*D
T #D_TID_1000
L #D_TID_TEMP
<>D
JCN A7e8
L #D_TID_1000
T #D_TID_TEMP
T #D_TID
A7e8: L #DB_CONT_C
T LW 42
L #D_TID
OPN DB [LW 42]
T DBD 28
L #TM_LAG
L #TM_LAG_TEMP
<>D
JCN A7e9
L #TM_LAG
T #TM_LAG_TEMP
L L#1000
/D
T #TM_LAG_OP
A7e9: L #TM_LAG_OP
L L#1000
*D
T #TM_LAG_1000
L #TM_LAG_TEMP
<>D
JCN A7ea
L #TM_LAG_1000
T #TM_LAG_TEMP
T #TM_LAG
A7ea: L #DB_CONT_C
T LW 42
L #TM_LAG
OPN DB [LW 42]
T DBD 32
L #DEADB_W
L #DEADB_W_TEMP
<>R
JCN A7eb
L #DEADB_W
T #DEADB_W_TEMP
T #DEADB_W_OP
A7eb: L #DEADB_W_OP
L #DEADB_W_TEMP
<>R
JCN A7ec
L #DEADB_W_OP
T #DEADB_W_TEMP
T #DEADB_W
A7ec: L #DB_CONT_C
T LW 42
L #DEADB_W
OPN DB [LW 42]
T DBD 36
TAK
T LW 42
OPN DB [LW 42]
CLR
A DBX 0.3
= #Q_P_SEL
T LW 42
OPN DB [LW 42]
A DBX 0.4
= #Q_I_SEL
T LW 42
OPN DB [LW 42]
A DBX 0.7
= #Q_D_SEL
SAVE
BE

A rather large amount of code so do not expect someone to have the time/effort to help us but thought it would be worth a shot

Kind regards,
Olle Z

joseph_e2 · Oct 2, 2023

If the original is in Step 7 Classic (Simatic Manager), it will convert the code to different languages if it can.

Is this all one network? If so, try breaking it up into a bunch of networks where you see "output" instructions. Like =, JCN, T, etc. That will get you closer at least.

L D[AR2P#0.0] · Oct 3, 2023

As a minimum you need to post the code as source code so the interface and data types are shown.

L D[AR2P#0.0] · Oct 3, 2023

First few lines converted to SCL - you should be able to see the pattern to follow.

Code:

 AUT_EXT_PULS_P:=NOT AUT_EXT_PULSM_P AND AUT_EXT;
 AUT_EXT_PULSM_P:=AUT_EXT;
 IF AUT_EXT_PULS_P THEN 
    MAN_AUTO:=True;
 END_IF;
 
 WORD_TO_BLOCK_DB(DB_CONT_C).DX[1]:=NOT MAN_AUTO OR TRK_ON;
 QAUTO:=MAN_AUTO; 
 QMAN:=NOT QAUTO;
 QTRK:=TRK_ON AND MAN_AUTO;
 
 IF TRK_ON AND MAN_AUTO THEN 
   WORD_TO_BLOCK_DB(DB_CONT_C).DD[16]:=REAL_TO_DWORD(TRK_VAL);
 ELSE
    WORD_TO_BLOCK_DB(DB_CONT_C).DD[16]:=REAL_TO_DWORD(MAN_VAL);  
 END_IF;

Olledvin · Oct 3, 2023

L D[AR2 said:

First few lines converted to SCL - you should be able to see the pattern to follow.

Code:

 AUT_EXT_PULS_P:=NOT AUT_EXT_PULSM_P AND AUT_EXT;
 AUT_EXT_PULSM_P:=AUT_EXT;
 IF AUT_EXT_PULS_P THEN 
    MAN_AUTO:=True;
 END_IF;
 
 WORD_TO_BLOCK_DB(DB_CONT_C).DX[1]:=NOT MAN_AUTO OR TRK_ON;
 QAUTO:=MAN_AUTO; 
 QMAN:=NOT QAUTO;
 QTRK:=TRK_ON AND MAN_AUTO;
 
 IF TRK_ON AND MAN_AUTO THEN 
   WORD_TO_BLOCK_DB(DB_CONT_C).DD[16]:=REAL_TO_DWORD(TRK_VAL);
 ELSE
    WORD_TO_BLOCK_DB(DB_CONT_C).DD[16]:=REAL_TO_DWORD(MAN_VAL);  
 END_IF;

Hi, thank you for the reply and massively appreciated that you converted a snippet of the block. As I am new (have not really worked with STL) it helps a lot to be able to compare the same logic in SCL and see the patterns as you say.

Thank you!

Kind regards,
Olle

Olledvin · Oct 3, 2023

joseph_e2 said:
If the original is in Step 7 Classic (Simatic Manager), it will convert the code to different languages if it can.

Is this all one network? If so, try breaking it up into a bunch of networks where you see "output" instructions. Like =, JCN, T, etc. That will get you closer at least.

Hi Joesph,

Yes, the original is in Step 7 Classic. Do you mean it could try to convert it if imported/migrated to TIA portal?

It is all in one network, yes. Good tip about splitting it up between instructions, thank you!

Kind regards,
Olle

Olledvin · Oct 3, 2023

Source Code:

VAR_INPUT
DB_CONT_C : WORD ; //REGULATORNS DB
PV_HLM : REAL ; //ÖVRE ÄRVÄRDESGRÄNS
PV_LLM : REAL ; //UNDRE ÄRVÄRDESGRÄNS
SP_EXT : REAL ; //EXTERNT BÖRVÄRDE
SP_HLM : REAL ; //ÖVRE BÖRVÄRDESGRÄNS
SP_LLM : REAL ; //UNDRE BÖRVÄRDESGRÄNS
LMN_HLM : REAL ; //ÖVRE UTSIGNALGRÄNS
LMN_LLM : REAL ; //UNDRE UTSIGNALGRÄNS
TRK_VAL : REAL ; //TRACKING VALUE
TRK_ON : BOOL ; //SÄTTER REGULATORN TILL TRACKING_VALUE
EXT_FEL : BOOL ; //EXTERNT FEL
ALM_SUP : BOOL ; //UNDERTRYCK LARM 1=UNDERTRYCKNING
AUT_EXT : BOOL ; //EXTERN ORDER ATT SÄTTA REGULATORN I AUTO
ALM_DELAY_ON : BOOL ; //FÖRDRÖJ LARM 1sek 1=FÖRDRÖJNING
END_VAR
VAR_OUTPUT
QPVH_LARM : BOOL ;
QPVL_LARM : BOOL ;
QPVH_VARN : BOOL ;
QPVL_VARN : BOOL ;
QEXT_FEL : BOOL ;
END_VAR
VAR_IN_OUT
PVH_ALM : REAL ; //LARMGRÄNS HÖG ALARM PV
PVL_ALM : REAL ; //LARMGRÄNS LAG ALARM PV
PVH_WRN : REAL ; //LARMGRÄNS HÖG VARNING PV
PVL_WRN : REAL ; //LARMGRÄNS LAG VARNING PV
HYSTERES : REAL ; //HYSTERES FÖR LARMER
GAIN : REAL ; //FÖRSTÄRKNING
DEADB_W : REAL ; //DÖDBAND
I_TID : TIME ; //I-TID
D_TID : TIME ; //D-TID
TM_LAG : TIME ; //TIME-LAG
END_VAR
VAR
RESERV1 : BOOL ; //BIT24
RESERV2 : BOOL ; //BIT25
RESERV3 : BOOL ; //BIT26
RESERV4 : BOOL ; //BIT27
RESERV5 : BOOL ; //BIT28
RESERV6 : BOOL ; //BIT29
RESERV7 : BOOL ; //BIT30
RESERV8 : BOOL ; //BIT31
RESERV9 : BOOL ; //BIT16
RESERV10 : BOOL ; //BIT17
RESERV11 : BOOL ; //BIT18
RESERV12 : BOOL ; //BIT19
RESERV13 : BOOL ; //BIT20
RESERV14 : BOOL ; //BIT21
RESERV15 : BOOL ; //BIT22
RESERV16 : BOOL ; //BIT23
RESERV17 : BOOL ; //BIT8
RESERV18 : BOOL ; //BIT9
RESERV19 : BOOL ; //BIT10
RESERV20 : BOOL ; //BIT11
RESERV21 : BOOL ; //BIT12
RESERV22 : BOOL ; //BIT13
RESERV23 : BOOL ; //BIT14
RESERV24 : BOOL ; //BIT15
MAN_AUTO : BOOL ; //BIT0 //MAN=0, AUTO=1
SP_INT_EXT : BOOL ; //BIT1 //INTERNT=0 / EXTERNT
RESERV25 : BOOL ; //BIT2
RESERV26 : BOOL ; //BIT3
RESERV27 : BOOL ; //BIT4
RESERV28 : BOOL ; //BIT5
RESERV29 : BOOL ; //BIT6
RESERV30 : BOOL ; //BIT7
EXT_OK : BOOL ; //BIT24 //EXTERNT FEL OK
EXT_ACK : BOOL ; //BIT25 //EXTERNT FEL KVITTER
RESERV41 : BOOL ; //BIT26
RESERV42 : BOOL ; //BIT27
RESERV43 : BOOL ; //BIT28
RESERV44 : BOOL ; //BIT29
RESERV45 : BOOL ; //BIT30
RESERV46 : BOOL ; //BIT31
PVHA_OK : BOOL ; //BIT16 //HÖG ALARM PV OK
PVHA_ACK : BOOL ; //BIT17 //HÖG ALARM PV KVITTE
PVLA_OK : BOOL ; //BIT18 //LAG ALARM PV OK
PVLA_ACK : BOOL ; //BIT19 //LAG ALARM PV KVITTE
PVHW_OK : BOOL ; //BIT20 //HÖG VARNING PV OK
PVHW_ACK : BOOL ; //BIT21 //HÖG VARNING PV KVIT
PVLW_OK : BOOL ; //BIT22 //LAG VARNING PV OK
PVLW_ACK : BOOL ; //BIT23 //LAG VARNING PV KVIT
RESERV33 : BOOL ; //BIT8
RESERV34 : BOOL ; //BIT9
RESERV35 : BOOL ; //BIT10
RESERV36 : BOOL ; //BIT11
RESERV37 : BOOL ; //BIT12
RESERV38 : BOOL ; //BIT13
RESERV39 : BOOL ; //BIT14
RESERV40 : BOOL ; //BIT15
QTRK : BOOL ; //BIT0 //TRACKING AKTIV
QMAN : BOOL ; //BIT1 //MANUELL MODE AKTIV
QAUTO : BOOL ; //BIT2 //AUTO AKTIV
Q_P_SEL : BOOL ; //BIT3 //PROPOTIONAL ACTION
Q_I_SEL : BOOL ; //BIT4 //INTEGRAL ACTION ON
Q_D_SEL : BOOL ; //BIT5 //DERIVATIVE ACTION O
RESERV31 : BOOL ; //BIT6
RESERV32 : BOOL ; //BIT7
RESERV47 : DWORD ;
PV : REAL ; //ÄRVÄRDE
SP_INT : REAL ; //INTERNT BÖRVÄRDE
SP_AKT : REAL ; //AKTIVT BÖRVÄRDE
LMN : REAL ; //UTSIGNAL
MAN_VAL : REAL ; //MANUAL VALUE
SP_EXT_OP : REAL ; //EXTERNT BÖRVÄRDE VISAS
SP_HLM_OP : REAL ; //ÖVRE BÖRVÄRDESGRÄNS VISAS
SP_LLM_OP : REAL ; //UNDRE BÖRVÄRDESGRÄNS VISAS
LMN_HLM_OP : REAL ; //ÖVRE UTSIGNALGRÄNS VISAS
LMN_LLM_OP : REAL ; //UNDRE UTSIGNALGRÄNS VISAS
PV_HLM_OP : REAL ; //ÖVRE ÄRVÄRDESGRÄNS
PV_LLM_OP : REAL ; //UNDRE ÄRVÄRDESGRÄNS
PVH_ALM_OP : REAL ; //LARMGRÄNS HÖG ALARM PV FRAN OP
PVL_ALM_OP : REAL ; //LARMGRÄNS LAG ALARM PV FRAN OP
PVH_WRN_OP : REAL ; //LARMGRÄNS HÖG VARNING PV FRAN OP
PVL_WRN_OP : REAL ; //LARMGRÄNS LAG VARNING PV FRAN OP
HYST_OP : REAL ; //HYSTERES FÖR LARMGRÄNSER FRAN OP
GAIN_OP : REAL ; //FÖRSTÄRKNING FRAN OP
I_TID_OP : DINT ; //I-TID FRAN OP
D_TID_OP : DINT ; //D-TID FRAN OP
TM_LAG_OP : DINT ; //TIME-LAG FRAN OP
DEADB_W_OP : REAL ; //DÖDBAND FRAN OP
PVH_ALM_TEMP : REAL ; //TEMPORÄRA VARIABLER
PVL_ALM_TEMP : REAL ;
PVH_WRN_TEMP : REAL ;
PVL_WRN_TEMP : REAL ;
HYST_TEMP : REAL ;
GAIN_TEMP : REAL ;
I_TID_TEMP : TIME ;
D_TID_TEMP : TIME ;
TM_LAG_TEMP : TIME ;
DEADB_W_TEMP : REAL ;
PVH_LARM : BOOL ; //HÖG ALARM PV
PVHA_PULS_P : BOOL ; //PULS HÖG ALARM GAR TILL
PVHA_PULSM_P : BOOL ;
PVHA_PULS_N : BOOL ; //PULS HÖG ALARM GAR FRAN
PVHA_PULSM_N : BOOL ;
PVL_LARM : BOOL ; //LAG ALARM PV
PVLA_PULS_P : BOOL ; //PULS LAG ALARM GAR TILL
PVLA_PULSM_P : BOOL ;
PVLA_PULS_N : BOOL ; //PULS LAG ALARM GAR FRAN
PVLA_PULSM_N : BOOL ;
PVH_VARN : BOOL ; //HÖG VARNING PV
PVHW_PULS_P : BOOL ; //PULS HÖG VARNING GAR TILL
PVHW_PULSM_P : BOOL ;
PVHW_PULS_N : BOOL ; //PULS HÖG VARNING GAR FRAN
PVHW_PULSM_N : BOOL ;
PVL_VARN : BOOL ; //LAG VARNING PV
PVLW_PULS_P : BOOL ; //PULS LAG VARNING GAR TILL
PVLW_PULSM_P : BOOL ;
PVLW_PULS_N : BOOL ; //PULS LAG VARNING GAR FRAN
PVLW_PULSM_N : BOOL ;
EXT_LARM : BOOL ; //EXTERNT FEL ALARM
EXT_PULS_P : BOOL ; //PULS EXTERNT FEL GAR TILL
EXT_PULSM_P : BOOL ;
EXT_PULS_N : BOOL ; //PULS EXTERNT FEL GAR FRAN
EXT_PULSM_N : BOOL ;
AUT_EXT_PULS_P : BOOL ; //PULS AUTO EXTERN
AUT_EXT_PULSM_P : BOOL ;
DELAY_PVHA : INT ; //RÄKNEMINNE FÖR LARMFÖRDRÖJNING
DELAY_PVLA : INT ; //RÄKNEMINNE FÖR LARMFÖRDRÖJNING
DELAY_PVHW : INT ; //RÄKNEMINNE FÖR LARMFÖRDRÖJNING
DELAY_PVLW : INT ; //RÄKNEMINNE FÖR LARMFÖRDRÖJNING
END_VAR
VAR_TEM
SDNotused : INT ;
RETUR_0 : INT ;
RETUR_1 : INT ;
RETUR_2 : INT ;
RETUR_3 : INT ;
RETUR_4 : INT ;
RETUR_10 : INT ;
RETUR_11 : INT ;
RETUR_12 : INT ;
RETUR_13 : INT ;
RETUR_14 : INT ;
SP_TEMP : REAL ;
I_TID_1000 : DINT ;
D_TID_1000 : DINT ;
TM_LAG_1000 : DINT ;
END_VAR

Olledvin · Oct 3, 2023

BEGIN
NETWORK
TITLE =SCL network
//compiled by SCL compiler version: SCL K5.1.5.1 (C5.1.9.17)
SET ;
SAVE ;
= L 40.1;
A #AUT_EXT_PULSM_P;
NOT ;
A #AUT_EXT;
= #AUT_EXT_PULS_P;
A #AUT_EXT;
= #AUT_EXT_PULSM_P;
A #AUT_EXT_PULS_P;
JCN A7d0;
SET ;
= #MAN_AUTO;

A7d0: L #DB_CONT_C;
T LW 42;
CLR ;
A #MAN_AUTO;
NOT ;
O #TRK_ON;
OPN DB [LW 42];

= DBX 0.1;

A #MAN_AUTO;
= #QAUTO;

NOT ;
= #QMAN;
A #TRK_ON;
A #MAN_AUTO;
= #QTRK;

A #TRK_ON;
A #MAN_AUTO;
JCN A7d1;
T LW 42;
L #TRK_VAL;
OPN DB [LW 42];
T DBD 16;
JU A7d2;
A7d1: L #DB_CONT_C;
T LW 42;
L #MAN_VAL;
OPN DB [LW 42];
T DBD 16;
A7d2: CLR ;
A #SP_INT_EXT;
JCN A7d3;
L #SP_EXT;
T #SP_TEMP;
JU A7d4;
A7d3: L #SP_INT;
T #SP_TEMP;
A7d4: L #SP_TEMP;
L #SP_HLM;
>R ;
JCN A7d5;
T #SP_TEMP;
T #SP_INT;
JU A7d7;
A7d5: L #SP_TEMP;
L #SP_LLM;
<R ;
JCN A7d7;
T #SP_TEMP;
T #SP_INT;
A7d7: CLR ;
A #SP_INT_EXT;
JCN A7d8;
L #SP_TEMP;
T #SP_INT;
A7d8: L #DB_CONT_C;
T LW 42;
L #SP_TEMP;
OPN DB [LW 42];
T DBD 6;
TAK ;
T LW 42;
OPN DB [LW 42];
L DBD 6;
T #SP_AKT;
L #SP_EXT;
T #SP_EXT_OP;
L #SP_HLM;
T #SP_HLM_OP;
L #SP_LLM;
T #SP_LLM_OP;
L #DB_CONT_C;
T LW 42;
OPN DB [LW 42];
L DBD 92;
T #PV;
L #PV_HLM;
T #PV_HLM_OP;
L #PV_LLM;
T #PV_LLM_OP;
L #DB_CONT_C;
T LW 42;
OPN DB [LW 42];
L DBD 72;
T #LMN;
TAK ;
T LW 42;
L #LMN_HLM;
OPN DB [LW 42];
T DBD 40;
TAK ;
T LW 42;
L #LMN_LLM;
OPN DB [LW 42];
T DBD 44;
L #LMN_HLM;
T #LMN_HLM_OP;
TAK ;
T #LMN_LLM_OP;
L #PVH_ALM;
L #PVH_ALM_TEMP;
<>R ;
JCN A7d9;
L #PVH_ALM;
T #PVH_ALM_TEMP;
T #PVH_ALM_OP;
A7d9: L #PVH_ALM_OP;
L #PVH_ALM_TEMP;
<>R ;
JCN A7da;
L #PVH_ALM_OP;
T #PVH_ALM_TEMP;
T #PVH_ALM;
A7da: L #PVL_ALM;
L #PVL_ALM_TEMP;
<>R ;
JCN A7db;
L #PVL_ALM;
T #PVL_ALM_TEMP;
T #PVL_ALM_OP;
A7db: L #PVL_ALM_OP;
L #PVL_ALM_TEMP;
<>R ;
JCN A7dc;
L #PVL_ALM_OP;
T #PVL_ALM_TEMP;
T #PVL_ALM;
A7dc: L #PVH_WRN;
L #PVH_WRN_TEMP;
<>R ;
JCN A7dd;
L #PVH_WRN;
T #PVH_WRN_TEMP;
T #PVH_WRN_OP;
A7dd: L #PVH_WRN_OP;
L #PVH_WRN_TEMP;
<>R ;
JCN A7de;
L #PVH_WRN_OP;
T #PVH_WRN_TEMP;
T #PVH_WRN;
A7de: L #PVL_WRN;
L #PVL_WRN_TEMP;
<>R ;
JCN A7df;
L #PVL_WRN;
T #PVL_WRN_TEMP;
T #PVL_WRN_OP;
A7df: L #PVL_WRN_OP;
L #PVL_WRN_TEMP;
<>R ;
JCN A7e0;
L #PVL_WRN_OP;
T #PVL_WRN_TEMP;
T #PVL_WRN;
A7e0: L #HYSTERES;
L #HYST_TEMP;
<>R ;
JCN A7e1;
L #HYSTERES;
T #HYST_TEMP;
T #HYST_OP;
A7e1: L #HYST_OP;
L #HYST_TEMP;
<>R ;
JCN A7e2;
L #HYST_OP;
T #HYST_TEMP;
T #HYSTERES;
A7e2: L #GAIN;
L #GAIN_TEMP;
<>R ;
JCN A7e3;
L #GAIN;
T #GAIN_TEMP;
T #GAIN_OP;
A7e3: L #GAIN_OP;
L #GAIN_TEMP;
<>R ;
JCN A7e4;
L #GAIN_OP;
T #GAIN_TEMP;
T #GAIN;
A7e4: L #DB_CONT_C;
T LW 42;
L #GAIN;
OPN DB [LW 42];
T DBD 20;
L #I_TID;
L #I_TID_TEMP;
<>D ;
JCN A7e5;
L #I_TID;
T #I_TID_TEMP;
L L#1000;
/D ;
T #I_TID_OP;
A7e5: L #I_TID_OP;
L L#1000;
*D ;
T #I_TID_1000;
L #I_TID_TEMP;
<>D ;
JCN A7e6;
L #I_TID_1000;
T #I_TID_TEMP;
T #I_TID;
A7e6: L #DB_CONT_C;
T LW 42;
L #I_TID;
OPN DB [LW 42];
T DBD 24;
L #D_TID;
L #D_TID_TEMP;
<>D ;
JCN A7e7;
L #D_TID;
T #D_TID_TEMP;
L L#1000;
/D ;
T #D_TID_OP;
A7e7: L #D_TID_OP;
L L#1000;
*D ;
T #D_TID_1000;
L #D_TID_TEMP;
<>D ;
JCN A7e8;
L #D_TID_1000;
T #D_TID_TEMP;
T #D_TID;
A7e8: L #DB_CONT_C;
T LW 42;
L #D_TID;
OPN DB [LW 42];
T DBD 28;
L #TM_LAG;
L #TM_LAG_TEMP;
<>D ;
JCN A7e9;
L #TM_LAG;
T #TM_LAG_TEMP;
L L#1000;
/D ;
T #TM_LAG_OP;
A7e9: L #TM_LAG_OP;
L L#1000;
*D ;
T #TM_LAG_1000;
L #TM_LAG_TEMP;
<>D ;
JCN A7ea;
L #TM_LAG_1000;
T #TM_LAG_TEMP;
T #TM_LAG;
A7ea: L #DB_CONT_C;
T LW 42;
L #TM_LAG;
OPN DB [LW 42];
T DBD 32;
L #DEADB_W;
L #DEADB_W_TEMP;
<>R ;
JCN A7eb;
L #DEADB_W;
T #DEADB_W_TEMP;
T #DEADB_W_OP;
A7eb: L #DEADB_W_OP;
L #DEADB_W_TEMP;
<>R ;
JCN A7ec;
L #DEADB_W_OP;
T #DEADB_W_TEMP;
T #DEADB_W;
A7ec: L #DB_CONT_C;
T LW 42;
L #DEADB_W;
OPN DB [LW 42];
T DBD 36;
TAK ;
T LW 42;
OPN DB [LW 42];
CLR ;
A DBX 0.3;
= #Q_P_SEL;
T LW 42;
OPN DB [LW 42];
A DBX 0.4;
= #Q_I_SEL;
T LW 42;
OPN DB [LW 42];
A DBX 0.7;
= #Q_D_SEL;

SAVE ;
BE ;
END_FUNCTION_BLOCK

JRW · Oct 3, 2023

Any chance of finding the original project?
(That contains the scl source)

That code was written in scl originally, not stl

Olledvin · Oct 3, 2023

JRW said:
Any chance of finding the original project?
(That contains the scl source)

That code was written in SCL originally, not stl

Aha, so then converted into STL for this S7 Classic project... I see.

It was written 15 years ago by a colleague who quit about 10 years ago... So probably not but worth a shot for sure.

Thanks for the tip!

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