suppose that you have a CTU with a Preset of 6 ... and the Accumulator is currently equal to 5 ... the Done bit is OFF ...
now suppose that the Preset is changed to 2 ... the Accumulator remains at 5 ... when you do that, the Done bit WILL come ON ...
now suppose that the Preset is changed back to 6 ... the Accumulator remains at 5 ... when you do that, the Done bit WILL go OFF ...
going further ...
suppose that the Accumulator has already reached its maximum value of 32,767 ... the Preset is at 6 ... the Done bit is ON ...
now the input causes one more count ... the Accumulator will “roll-over” to -32,768 ... note the negative sign ... the Done bit will stay ON ... the counter’s OV (overflow) bit (example: C5:0/OV) will come ON ...
now suppose that more and more counts keep coming in ... the Accumulator will eventually get back into positive numbers ... all of this time the Done bit will stay ON ... for all practical purposes, the counter has now been “broken” by the overflow (roll-over) condition ... the Done bit will basically stay on until something external (example: an RES) resets it ...
note that the counter’s OV bit is NOT the same as the processor’s “overflow Trap” bit (S:5/0) ... specifically, the “roll-over” of the counter (and the subsequent setting of its OV bit) will NOT fault the processor ... I think that here you are confusing the operation of a math operation (example: and ADD) which tries to store a “too-large” number in an integer location ... the counter doesn’t do the same thing ...
and yes, I just tried and confirmed all of this on a spare SLC-5/04 in the lab ...