My controllogix PLC uses a start output and a stop output to start and stop a motor respectively. The start and stop output is a 5 sec pulse.
The attached picture is my way of implementing the logic. When bit[0],1 or 2 turns on, it triggers the OSR instruction. The output bit of the OSR instruction latches on the TON timer to provides a 5 sec pulse output. When rung 0 is false (bits 0,1,2 are off), the OSF instruction latches on TM[1] to produce a stop signal. Tm[1].tt is tied to stop signal output and tm[0].tt is tied to the start signal output.
Is there a better way to implement the logic described above? Are any potential problems with the logic?
The attached picture is my way of implementing the logic. When bit[0],1 or 2 turns on, it triggers the OSR instruction. The output bit of the OSR instruction latches on the TON timer to provides a 5 sec pulse output. When rung 0 is false (bits 0,1,2 are off), the OSF instruction latches on TM[1] to produce a stop signal. Tm[1].tt is tied to stop signal output and tm[0].tt is tied to the start signal output.
Is there a better way to implement the logic described above? Are any potential problems with the logic?