What does this input do in this ladder logic?

[shaydzmi]

I have this program:
ZIP (.rss inside no documentation)
PDF (Italian documentation)
Allen Bradley SLC5/03 PLC.

Running on a machine, I want to know how the input (I:3/2) does its job which is stopping the machine when the gate is open.

I see it's related(??) to the (N7:51/5) , but it goes nowhere after that. I searched for N7:51/5 I found it only in one place no where else.

The PLC is connected to an HMI, but it works without it, I mean the machine stops when the gate is open even when the HMI is disconnected from it.

If more info is needed tell me! Thank you.

 

[arpus4KM]

I have this program:
ZIP (.rss inside no documentation)
PDF (Italian documentation)
Allen Bradley SLC5/03 PLC.

Running on a machine, I want to know how the input (I:3/2) does its job which is stopping the machine when the gate is open.

I see it's related(??) to the (N7:51/5) , but it goes nowhere after that. I searched for N7:51/5 I found it only in one place no where else.

The PLC is connected to an HMI, but it works without it, I mean the machine stops when the gate is open even when the HMI is disconnected from it.

If more info is needed tell me! Thank you.

N7:51 in LAD 3, rung 33

the N7:51 is being compared NEQ to 0. so when you turn on any bit in N7:51 the bit b3:1/14 turns on, which leads to rung 35. which then leads to LAD 2, rung 7 XIO B3:1/11.... which i'm assuming is something to do with your latched run circuit.

 

[drbitboy]

In [LAD 3 ALLARMI] Rung 0033, N7:51 is tested against 0. If any bit in N7:51 is 1, e.g. N7:51/5 (value 32) because I:3/2 was 0 when Rung 0018 was evaluated, then the [NEQ N7:51 0] instruction's output rung will be 1 and [Aux segnalazio allarmi B3:1/14] will be assigned a 1, which will result in [Aux arresto macchina per inter. allarmi B3:1/11] being assigned a value of 1 on Rung 0035, which is a Stop condition [XIO B3:1/11] in the Start/Stop Circuit pattern on Rung 0007 in [LAD 2].

[Update: I'm too slow!]

 

[shaydzmi]

Thank you IanM8040 and drbitboy..

[Update: I'm too slow!]

Slow but you gave more information!

Now I understand, but why did they do this complicated way instead of putting all bits in series like in an actual circuit?

 

[OkiePC]

---

Now I understand, but why did they do this complicated way instead of putting all bits in series like in an actual circuit?

It looks like there are 3 words being dealt with here as 'shutdown faults' so to speak. That would mean 48 XIO instructions in series, or three rungs each with up to 16 instructions each and then another rung to combine those results in order to get the equivalent logic with bit compares rather than word compares.

It would be uglier to look at, but actually execute faster that way. It basically comes down to a style preference because ugly is in the eye of the beholder.

 

[drbitboy]

Thank you ...

And thank you for an excellent Post #1 of this thread (RSS + PDF - I found the answer by searching for N7:51 in the PDF); it made it easy to find.

 

[shaydzmi]

It looks like there are 3 words being dealt with here as 'shutdown faults' so to speak. That would mean 48 XIO instructions in series, or three rungs each with up to 16 instructions each and then another rung to combine those results in order to get the equivalent logic with bit compares rather than word compares.

It would be uglier to look at, but actually execute faster that way. It basically comes down to a style preference because ugly is in the eye of the beholder.

I'm confused! which one is faster and which is ugly? (I'm beginner in PLCs + English is my 3rd language).