PLC5 PID after processor upgrade

If N407:75 value > 1 then PD9:29 SP = 4095
(Am I right or was I being inattentive again?)

If so, then in #39 block diagram, PID controllers have no information about the tank-level


agreed.


Howevever, if a value is written to N347:10 (e.g. BTR instruction) after write PD9:29 writes to N347:10 and the next time PD9:29 runs again, then situation is different.
 
Howevever, if a value is written to N347:10 (e.g. BTR instruction) after write PD9:29 writes to N347:10 and the next time PD9:29 runs again, then situation is different.

I.e. block diagram (N407:75>1) looks like below? (this is the only way I can imagine of to make the system work)

I suppose #4 above PID PD 9:13 "construction" is to prevent conveyor speed decreasing when level N407:75<1

twoPIDFB.png
 
If N407:75 value > 1 then PD9:29 SP = 4095
(Am I right or was I being inattentive again?)

If so, then in #39 block diagram, PID controllers have no information about the tank-level

PD9:29.SP is N407:75 which is a 4-20ma sensor whose signal varies with each deposit due to how the hopper moves when depositing. The signal I think is 4ma when empty and 20ma when full. The signal is coming from a BTR of a 1794-IE8
 
PD9:29.SP is N407:75 which is a 4-20ma sensor whose signal varies with each deposit due to how the hopper moves when depositing. The signal I think is 4ma when empty and 20ma when full. The signal is coming from a BTR of a 1794-IE8

#4 2 rungs above PID PD9:29
 

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