The PLC will be obeying exactly whatever instructions it is given to operate. You have to start from the belief that the CPU is operating correctly. If you give up that belief then you have nothing to go on!
If we assume that it is working OK, you now have to look through the ladder and investigate exactly why the logic behaves as it does rather than as you expect. Clearly your expectations are wrong here, because the PLC is behaving otherwise. To allow us to help you still requires more details.
Statements like "The enable/rest will not reset" need clarification. Do you mean the contact assigned to the "Enable/Reset" input on the function stays permanently in one logic state, presumably a "1", enabling the SHRB? Or do you mean that it can be moved between "1", enable, and "0", reset, but there appears to be no effect on the contents of the shift register? Let's take the former as the first path of investigation. If a bit won't change state, is it forced? If it is, why? Don't always assume that unforcing it will fix everything - it may reveal another bigger problem that was the reason for the force in the first place! If it's not forced start working through the rest of the ladder to see where this bit may be controled. This has to include direct intentional control as a coil, or inadvertant control due to being part of MWIR instruction or similar. Unfortunately the whole process of debugging a program can be tedious and nit-picking. Keep an open mind and don't make any assumptions.
Post your code, or provide really specific descriptions of the structure, problems, symptoms etc. The TI support here relies heavily on the two Kens, but fortunately I get the impression we both just about know what we're talking about. So far I think we've dug most people out of the holes they've been in.
Regards
Ken