another scan time question compactlogix

If an element on a rung is false, does that shorten the scan time, as it does not need to execute anything on the rung after that?

similarly, if there is a jump to label, that is executed and the logic between them is skipped, does that shorten scan time?

thank you

Yes it will decrease scan time although it does actually continue through the rung. It will continue through as that is required to set the output false. For example, imagine a rung that has four inputs. We'll call them A,B,C, and D. Plus one output that we will call "X". Here is an example of how that logic might get scanned:

1. Start Rung with True state
2. Check Input A for True/False
3. Input A is True, continue in a True state to B
4. Check Input B for True/False
5. Input B is True, continue in a True state to C
6. Check Input C for True/False
7. Input C is False, continue in a False state to D
8. Don't check Input D, continue in a False state to X
9. Set Output X to False
10. End of Rung

So in this case there is a minimal scan time savings in that the controller does not have to check to see if input D is true or false as it essentially says "I don't care" and moves on. But it has to continue scanning so that step #9 above happens.

A JUMP (JMP) skips to the LABEL (LBL). If that LBL is below the JMP then yes, logic is skipped, shortening scan time. If the LBL is above the JMP it can increase scan time (and potentially cause other issues as well) since it has to repeat logic.

OG

Sorry, got the picture in there twice.

realolman said:

If an element on a rung is false, does that shorten the scan time, as it does not need to execute anything on the rung after that?

similarly, if there is a jump to label, that is executed and the logic between them is skipped, does that shorten scan time?

thank you

Click to expand...

Your first question.... The program scan has to "execute" each and every instruction on a rung, even if the Rung Logic Continuity (RLC) has been made false by a false conditional instruction. Many instructions "react" to the RLC being false, in the same way that many "react" to the RLC being true. Just making a rung false does not guarantee a faster execution time, it totally depends on what instructions the processor encounters after RLC goes false.

Having said that, there are guidelines for instruction placement that can improve scan time. Place instructions that have the highest probability of being false, and thus turning the RLC false, at the beginning of a rung, subsequent conditional instructions do not have to interrogate the tag database, because the rung cannot be turned true again (branching obviously modifies this behaviour).... All the processor will be doing, once there are no open branches, is searching for instructions that it has to "react" to the RLC being false (e.g. OTE, TON, TOF, CTU, CTU, etc. etc.)

I could check, and so could you, the execution times for output instructions when the RLC is true, and when it is false. I'm guessing that nearly all execute faster when the RLC is false, but they must execute.


Your second question.... JMP to a (later) LBL will "skip" the code between them, so execution time will be faster, yes. But be aware that when you make the rung with the JMP true, all of the rungs between the JMP and the LBL will not be scanned, so any "outputs" within that skipped logic will freeze, OTE's will stay on, even if the rung conditions dictate they go off.

But be aware that when you make the rung with the JMP true, all of the rungs between the JMP and the LBL will not be scanned

Click to expand...

got it. thank you

I guess that's what I wanted in order to speed up the scan... there are routines having to do with operator input etc.... no point running those if the operator isn't inputting.