Combinational logic vs Sequential logic (Petrinets) in PLC

[Sioan]

You clearly did not understand what I said. I would suggest you read it again.

It's not so complicated as someoane may think !

 

[Vartile]

PIDs are a continuous process. Controlling temperature is a continuous process. In machine control there is a lot of "do this" "wait for this to be done" then "do that" then "wait for that to be done" then "do the next thing" then "wait for the next thing to be done" etc then repeat for the next part.

Vartile, can you see the difference between a PID and machine control?

Sioan is just trying to screw with your mind.

SFCs or Sequential Function Charts are basically Moore state machines. Once you are in a state you stay there until a transition has occurred to go to the next state. Our motion controller has a build in state machine that functions in a similar way to SFCs. It looks different but pretty much works the same way.

Yes, I see it. My point was that there is many mixed/hybrid control problems where there is need of both, state (on/off/limit-value) and continuous time. How usefull tool (isn't that what statemachine theory is?) statemachine are to those. That was directed mainly to Sioan.

Sure that a PID is a finite state machine (in a loop) ! ... isn't it DIGITAL ?

Yes, digital is discrete, if that is what you meant? Or did you mean that you calculate it step by step? or both?

So what is the difference in the two of the statemachines when someone actually implements the diagram to realworld. Can you give basic example?

How statemachine behaves in case of parallel/multitask routines?

I beg your pardon !
A (digital) PID is very well at a normal level a finite state machine : ( is a just a finite number of ... CPU instructions/states the ... PID)

How many lines of code need you for ...

someone have to really see the FSM states between the lines of his code ... to know about ... cybernetics

The line count depends on the language used (..if there is lines)? Can you give example of PID made out of statemachine diagrams?

This hang to diagram drawing theory of predesigning process doesn't go (yet) to my head. Because as far as I know you can't code with (pure)statemachine diagrams? If you don't count SFCs to pure/real ones.

The point is I'm sceptically interested and will be reading about them in the becoming weeks. I have implemented them 100% sure, but without knowing they have this fancy name (..or I just were sleeping in that part of course.). After that I could decide if I throw them to trash bin or archive between my ears. Piece.

 

[Peter Nachtwey]

Sioan is just pulling our chains.
First, Sioan hasn't backed up anything he has said.
Second, we have done well with Moore state machines.
Third, a PID doesn't have states. The system has states. I challenge Sioan to show me more than one state. Why? Well Sioan should know it takes only ONE of code to implement a PID.
Four, PID doesn't need to be digital. There were analog PIDs long before digital ones.

Vartile, motion control uses a PID continuously closes the loop but there are state machines that are used to move the target position or set point from one point to another at the right time. The actual moving the target position is also a state machine. There is the stopped state, ramping up state, constant velocity state and ramping down state for starters.

A digital PID is a filter, an Inifinite Impulse Response or IIR filter to be exact, not a state machine.

 

[Sioan]

There are FSMs and there are VFSMs , but from an abstract level the same principle (I think).
.... therefore you have internal in the code "inputs" and "outputs" ...etc.
(messages/"inputs" between (V)FSMs)
I'm sure you can implement a PID as a VFSM ( virtual finite state machine) ... is your choice !
What I spoke is not a DOGMA ... give me some against-spoken arguments !

I also think that you only need to implement concurency if you have a multiple procesors CPU .
For a single procesor CPU there is only the ilusion of ...concurency ...(these means you don't really need to implement it in code for a single procesor CPU , ).

Of course you can made everything "concurent" ... with lots of semaphores , timers , status flags , deadlocks ...etc.

look here

 

[Sioan]

To my statements , I have one thing ONLY to say:

- Every algorithm(!) can be represented as a (virtual)state machine.

 

[KalleOlsen]

Not much snow in Graz these days?

(you shouldn't eat those mushroms)





Dr. Watson

 

[Sioan]

Not much snow in Graz these days?

(you shouldn't eat those mushroms)





Dr. Watson

I am not ... Holmes

 

[L D[AR2P#0.0]]

- Every algorithm(!) can be represented as a (virtual)state machine.

I'd be very interested to see the state machine implementation of the algorithm used in the following function for calculating factorial.

FUNCTION FC 89 : DINT
TITLE =Factorial
VERSION : 0.1


VAR_INPUT
  x : DINT ;    
END_VAR
VAR_TEMP
  y : DINT ;    
  z : DINT ;    
END_VAR
BEGIN
NETWORK
TITLE =

      L     #x; 
      L     0; 
      ==D   ; 
      JC    ret1; 
      TAK   ; 
      L     1; 
      ==D   ; 
      JC    ret1; 
      L     #x; 
      +     L#-1; 
      T     #y; 
      CALL FC    89 (
           x                        := #y,
           RET_VAL                  := #z);
      L     #z; 
      L     #x; 
      *D    ; 
      T     #RET_VAL; 
      BEU   ; 
ret1: L     1; 
      T     #RET_VAL; 

END_FUNCTION

 

[Sioan]

a question of clarifying

Is a (digital) PID an ...?... algorithm ? ... gets it at all , continuously inputs ?

? ? ?

 

[Sioan]

@L D[AR2,P#0.0]
Say me how many (internal)states/steps has the function/algorithm and I'll do it !

 

[Sioan]

I'd be very interested to see the state machine implementation of the algorithm used in the following function for calculating factorial.
...

Can you try to post a correct Function/ALGORITHM , please ? Try to calculate 25!

 

[Vartile]

I can throw also that every algorithm can be made out of fluidic logic gates, but is it really usefull. That Is the main question here (was before and is now) I think without knowing the FSM theory too much. (readed the wiki articless so far. UML state machine implementation seems more interesting than generic FSMs in general).

I see some benefits of flowchart simplified machines (FSM) (..or old flowchart approach) in machine control. Is it usefull for hybrid machines/processes or plain continous processes in some level, that I'm interested and will find out.

To my statements , I have one thing ONLY to say:

- Every algorithm(!) can be represented as a (virtual)state machine.

..But I'm turning this thread to sidetrack, I'll go to read about FSMs.

 

[Sioan]

I'd be very interested to see the state machine implementation of the algorithm used in the following function for calculating factorial.

FUNCTION FC 89 : DINT
TITLE =Factorial
VERSION : 0.1


VAR_INPUT
  x : DINT ;    
END_VAR
VAR_TEMP
  y : DINT ;    
  z : DINT ;    
END_VAR
BEGIN
NETWORK
TITLE =

      [COLOR="Magenta"]L     #x;[/COLOR] 
      L     0; 
      ==D   ; 
      JC    ret1; 
      TAK   ; 
      L     1; 
      ==D   ; 
      JC    ret1; 
      L     #x; 
      +     L#-1; 
      T     #y; 
      CALL FC    89 (
           x                        := #y,
           RET_VAL                  := #z);
      L     #z; 
      L     #x; 
      *D    ; 
      [COLOR="Magenta"]T     #RET_VAL; [/COLOR]
      BEU   ; 
ret1: L     1; 
      [COLOR="Magenta"]T     #RET_VAL;[/COLOR]

END_FUNCTION

FUNCTION FC 89 : DINT
TITLE =Factorial
VERSION : 0.1
VAR_INPUT
  x : DINT ;	
END_VAR
VAR_TEMP
  y : DINT ;	
  z : DINT ;	
END_VAR
BEGIN
NETWORK
TITLE =
    [COLOR="Magenta"]  L     #x; [/COLOR]
      T     #y; [COLOR="Silver"]//y = x[/COLOR]
      T     #z; [COLOR="silver"]//z = x[/COLOR]
      L     1; 
      >I    ; 
      JCN   B; 
A:    L     #y; 
      +     L#-1; 
      T     #y; [COLOR="silver"]//y = y - 1[/COLOR]
      L     #z; 
      *D    ; 
      T     #z; [COLOR="Silver"]//z = z * y[/COLOR]
      L     #y; 
      L     L#1; 
      >I    ; 
      [COLOR="Blue"][B]JC    A; [/B][/COLOR]
      L     #z; 
      [COLOR="Magenta"]T     #RET_VAL; [/COLOR]
      BE    ; 
B:    L     L#1; 
      [COLOR="Magenta"]T     #RET_VAL;[/COLOR] 
END_FUNCTION

...should I explain ?

x -> input
RET_VAL -> output

 

[L D[AR2P#0.0]]

- Every algorithm(!) can be represented as a (virtual)state machine.

I was expecting you to show us how to do this for my recursive algorithm, not to modify it to be non-recursive.

How about posting your own algorithm and showing how you would generate the state machine. Please include implementations of both.

 

[Sioan]

There's just one algorithm for factorial ( not mine , not your) :

x! = x*(x-1)*(x-2) *...*(x-(x-1))
0!=1

"factorial" is just the name of this algorithm (make from some inputs some outputs ... thats the whole ... mathematics).
RECURSION is not the best for PLC ( ... needs match more time and procesor memory than the iteration) !

If I would write it as a FB I could show you , with a timer the states between ... Need you that ?