OK... I got this from the DL405 Manual...
Caution: The TMRA uses two consecutive timer locations, since the preset can now be 8 digits, which requires two V memory locations. For example, if TMRA T0 is used in the program, the next available timer is T2. Or if T0 was a normal timer, and T1 was an accumulating timer, then the next available timer would be T3.
What this means is... Timer Memory is assigned like so...
Timer Memory
Reference Address USAGE
T0 V0 T0 Standard
T1 V1 T1 TMRA - Word-1
T2 V2 T1 TMRA - Word-2 T2 is NOT available!
T3 V3 T3 Standard
T4 V4 T4 Standard
T5 V5 T5 TMRA - Word-1
T6 V6 T5 TMRA - Word-2 T6 is NOT available!
T7 V7 T7 TMRA - Word-1
T8 V8 T7 TMRA - Word-2 T8 is NOT available!
T9 V9 T9 Standard
T10 V10 T10 Standard
Next available Timer is T11
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This is the compacted version I spoke of earlier. This is nothing less than idiocy! They HAD to provide that "Caution"... it's to cover their short-sightedness!
However, in light of this, I can now see the rational behind using only the Even, or only the Odd Timers. Of course, that means that the total number of timers is cut in half at the git-go.
So... if there are 1000 Timer References available (T0 to T999) then you can have as many as 1000 Standard Timers, or as few as 500 Accumulating Timers, or some combination between 500 and 1000.
The basic design problem here is that AD has chosen to bind the Timer Reference Number, regardless of the timer-type, directly to a V-mem address. Bad move.
In effect, by referencing a particular timer number, the programmer references a specific location in Timer Memory. He then declares, by declaring the timer-type, how many locations are required for the particular timer. That would be 1 location for a Standard Timer, and 2 consecutive locations for an Accumulating Timer.
Having designed it this way, each Accumulating Timer Reference precludes the use of the next Timer Reference in sequence. If T0 is Accumulating, then the next timer in the sequence, T1, is not available. If the programmer references T1 then he is "stepping" on T0.
They could have done better. They could have taken one of two other approaches...
They could have built in a Timer Memory area for each type. That is, T0, T1, T2... and TA1, TA2, TA3... Then, you would have access to ALL of the particular timers without "stepping" across any timer boundary. Of course, depending on the number of available Timer References, that might mean that AD would have to add more memory for timers. Or, if there were only 1000 timer-memory locations, they could simply say... you can have up to 500 Standard Timers (T0 to T499) and up to 250 Accumulating Timers (TA0 to TA249).
Or, using only a single timer memory area, they could have had the timer memory locations dynamically allocated by timer-type. This is a tougher way to go, but it can be managed. It is, after all, the way the better systems manage "virtual memory". In this case, the processor recognizes the timer-reference and the declared timer-type. The processor maintains two look-up tables, one for Standard and one for Accumulating.
The processor then goes through the timer-memory area to find the first available slot that matches the type (1-location for Standard, or 2 consecutive locations for Accumulating). The processor then records that, or those, locations into the particular Timer Reference look-up table. At the same time, the timer-memory locations are "marked" as used. If a timer reference is removed from the program then the timer-memory locations associated with that timer is "unmarked" and made available for subsequent use. Then, that timer, in the particular look-up table, is cleared. In terms of memory usage, this is no worse than the existing scheme.
A "smart" programming package would be capable of detecting and indicating when you tried to use a timer that is already in use. Also, at each compile, the processor could compact the timer-memory area, while updating the look-up tables. This would make more 2-location slots available.
The benefits of either of these methods is that you would have access to ALL of the timer references AND you would not be capable of "stepping" on any other timers. Another benefit is that you would be able to access the data in each timer by timer reference as opposed to V-mem reference. That means that V0, V1, V2 etc. would be available for normal V-Mem use.
Granted... we all have to use our PLCs the way they were designed. But damn! AD sure could have done a much better job on this issue.