PLC Scan Cycle Question

Tim Ganz

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Dec 2010
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When using AB PLC's during the scan cycle instructions are scanned top to bottoma nd left to right correct? How does this work with instructions in branches?

Say my first rung is an XIC and it has 4 branches under it that also have 3 XIC's on each branch would the rung be scanned as my first main rung XIC fist then my first branch and first XIC on the left of that branch and then the other 2 will be scanned moving left to right then down to the next branch left to right unitl all are done?

Then it would hop to the next instruction to the right on the main rung and continue moving right until the end of the rung? Do I have this right?

Does it make a difference if it's a extended branch or a nested branch? Are they scanned the same way?
 
Also during the scan I have seen some teachings that say the system is looking at the bit table for a 1 or a 0 during the scan and I have seen some things say that the system takes a picture of the input and output bit tables as the scan begins and before the logic is solved and that the system looks to this picture of the bit table as reference for solving the logic.

Which is it?
 
You have it exactly right as you say in your first post. One way to see how this will be executed is to double-click on the rung number. The rung instructions will be listed at the top of the ladder. The PLC will process through the rung exactly as it is listed there.

The bit/data table is live during the scan. So if you change the value of any bit or tag by instruction, that change happens immediately and the new value will be used through the rest of the scan until it is changed again by a different instruction in the ladder. This is true regardless of ControlLogix, Compact Logix, SLC, or MicroLogix.

Where things get confusing is in the case of I/O information. For SLC's and MicroLogix platforms the physical inputs are checked once prior to the ladder execution and the input table is updated accordingly. The input table will not change through the ladder execution (unless you write an instruction to change it, which is a bad idea). During the ladder execution, the output table is updated according to your program. At the end of ladder execution the values in the output table are transferred to the outputs only once. They will not change again until the ladder has executed again.

On the newer ControlLogix and CompactLogix platforms, the I/O tables are updated independently from the ladder execution. This means that input values may change in the middle of a ladder execution so that an input bit may return a 1 on one rung and then return a 0 on the next.

Hope that makes sense.
 
But they don't seem to mention if the processor takes a snapshot / picture of the bit table before the logic is solved.

look at "Big Step Number I" again ... that's where it shows that the processor takes a "snapshot" of the input signals – and updates the bit/boxes on the Input Image Table with the status of ONES and ZEROS ...

In the demonstration it leads me to think the processor is always refering to the live bit table when solving the logic

that is correct ... the processor goes back to the bit/boxes to "read" the status ...

BUT ...

the input table doesn't get updated with "live" data from the field – until "Big Step Number I" rolls around again ...
 
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So only the processor only takes a snapshot of the input table before solving the logic and not the output table.

So N and B and T and C addresses can change mid scan and for that matter so can the output table?

Also how do you prevent contrologix inputs from changing mid scan? I have seen programs that do a CPS of local.Data.1 input card to DINT tag Local_Slot_1. But how does that keep it from changing mid scan?

If local.data.1.1 changed mid way though a large program it would change DINT tag Local_Slot_1.1 also correct?
 
So N and B and T and C addresses can change mid scan and for that matter so can the output table?
Yes. Check out my avatar. Any or all of the outputs could be almost anywhere in the data table, including the output image table.

As mentioned above, values will change during the program scan (else what would be the purpose?) and be immediately available for use elsewhere, even in the same rung. It's just that the output image table doesn't get sent to the physical addresses 'til after the program scan concludes - for the older PLC, SLC, types.
 
What a lot of people (including me) do to get around the Control Logix inputs changing asynchronously issue is to have the first called routine be a routine that maps all of the physical inputs (analog and digital) to tags. Then the next however many routines solve the logic, based on the tag status set by the input routine, and after all of that the last routine writes tags to all of the output addresses. This makes it function the same way as an older-style SLC/Micrologix controller. It has a lot of other advantages as well, there's a few threads on the topic on this forum. Of course, there are not that many scenarios in simple logic where it matters if your input image is updated halfway through a program scan. But if you're not sure, or if it DOES matter, that's a good way around it.

And yes, as alluded to in Doug's post - in a Micrologix/SLC, if you turn on an output bit (e.g. OTE O:1/2), then if the next rung has an XIC O:1/2, then it will be true. As soon as you turn on the output bit, the output data table is updated, and the rest of the logic knows that you turned it on. BUT, the physical output itself won't turn on right then. Once the PLC finishes scanning through the whole program, then it looks at the output data table and turns on or off each physical output to match what the output data table looked like at the end of the program scan. Then it goes and reads all the physical inputs, copies their status to the input data table, and starts solving the logic all over again from the top.
 

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