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Old December 14th, 2014, 06:45 PM   #1
Aabeck
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RSLogix Bit Toggling At Startup

I have used this Flip-Flop routine for years (see 1st picture) without incident, but noticed today while programming a flashing light sequence for my son's new Ghostbusters model car I put lights in, that the enabled bit shuts off every time the PLC is powered up or switched from Program to Run when it was on, and I think the bit should be retained & don't see how the One-Shot is getting activated. I even tried a XIO First-Scan so it wouldn't turn on the One-Shot at power-up, but it still shuts off.

I ended up adding a latched bit as shown in the 2nd picture to retain the proper state.

I noticed this on the Micrologix 1000 I was programming for my son, but I put the same ladder in a SLC5/04 & tested it & it shut off the bit on power-up also.

Am I missing something or is this normal?
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Old December 14th, 2014, 07:52 PM   #2
Ron Beaufort
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I'm not 100% sure that I'm following everything that you're reporting -

but -

whenever an Allen-Bradley processor has a "go to run" experience - each OTE instruction will go write a ZERO into its bit box ... this is a part of the PRE-SCAN operation ...

if you'll look at it that way it will probably start to make sense ...

NOTE: it's a little more complicated than that for a ControlLogix or CompactLogix system - but we'll skip that part since you're not working with either of those platforms ...
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Last edited by Ron Beaufort; December 14th, 2014 at 07:56 PM.
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Old December 14th, 2014, 07:57 PM   #3
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Quote:
Originally Posted by Ron Beaufort View Post
I'm not 100% sure that I'm following everything that you're reporting -

but -

whenever an Allen-Bradley processor has a "go to run" experience - each OTE instruction will go write a ZERO into its bit box ... this is a part of the PRE-SCAN operation ...

NOTE: it's a little more complicated than that for a ControlLogix or CompactLogix system - but we'll skip that part since you're not working with either of those platforms ...
So glad you corrected your original reply, Ron - I was halfway though correcting it for you when I noticed the edit.....
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Old December 14th, 2014, 08:04 PM   #4
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Quote:
Originally Posted by Ron Beaufort View Post
whenever an Allen-Bradley processor has a "go to run" experience - each OTE instruction will go write a ZERO into its bit box ... this is a part of the PRE-SCAN operation ...
Thanks, that explains it. I was thinking the bit status should be retained like bits set but not controlled by OTE's. But then shouldn't the 2nd ladder write a zero even if the latched bit is on - which it doesn't, it retains the state.

As for the ControlLogix, I do work on those too so could you explain the more complicated?
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Old December 14th, 2014, 08:31 PM   #5
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Originally Posted by Aabeck View Post
Thanks, that explains it. I was thinking the bit status should be retained like bits set but not controlled by OTE's. But then shouldn't the 2nd ladder write a zero even if the latched bit is on - which it doesn't, it retains the state.

As for the ControlLogix, I do work on those too so could you explain the more complicated?
The pre-scan does not change the state of any bits referenced by OTL/OTU instructions, only OTE.

I don't believe it is any different in Control/CompactLogix - the pre-scan simply resets any data-bits that are referenced by OTE instructions, and sets the storage bits for ONS instructions. I'm sure Ron will enlighten us if there are differences.

And just to make it clear, there is no such thing as a "latched bit". All processor memory is retentive by design, and bit locations are just written to 1 or 0 depending on the rung logic continuity as each instruction is scanned. The only thing that can turn a bit off is the pre-scan - or rung that evaluates as "false".
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Last edited by daba; December 14th, 2014 at 08:36 PM.
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Old December 14th, 2014, 08:38 PM   #6
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Quote:
So glad you corrected your original reply, Ron - I was halfway though correcting it for you when I noticed the edit.....
thanks ... good to know that someone has my back ... I'm working on putting together a little "dog and pony" show for Safety I/O in my "home" lab – and I don't multitask too well when I'm this tired ...

Quote:
As for the ControlLogix, I do work on those too so could you explain the more complicated?
I may have to correct this in the morning – but here's the general idea ...

first let's start with an SLC or MicroLogix system ...

suppose that you're using a LATCH (OTL) instruction – and an UNLATCH (OTU) instruction – and that both rungs are FALSE ...

suppose that the bit/box has a status of ONE when you shut down the system ...

when the system powers back up again (go to run) the bit/box should still have a ONE status ... it "retains" its status is how this operation is usually described ...

but suppose that you add another rung – even an UNconditional rung – with an OTE instruction for the same bit address – and that you place this rung in an UNUSED subroutine ... specifically, the subroutine has NO way to be executed ... no JSR – no STI – no DII – no "NUTHIN" to tell the processor to scan/execute the OTE rung ...

(some programmers create a "scrap pile" subroutine – and "park" unused rungs in it – just in case they might need them later) ...

now when you power down – and back up – or go to program mode and then back to run mode (go to run) – the LATCH bit will NOT retain its ON status ... specifically, PRE-SCAN will find that "UNUSED" (orphan) OTE instruction – and go write a ZERO into the bit/box ... in other words, the LATCHED bit "won't hold" its ONE status ...

now for a ControlLogix or CompactLogix system ...

suppose that we set up the same test as before ...

now when you power down – and back up – or go to program mode and then back to run mode (go to run) – the LATCH bit WILL retain its ON status ... specifically, PRE-SCAN operation will NOT find and execute that "UNUSED" subroutine ... in this case, the LATCHED bit "will hold" its ONE status (at go to run) ...

that's the basic difference that I was referring to earlier ...

now add a JSR rung to "call" the unused subroutines in each of the systems – and make both of the JSR rungs FALSE ... for example: use an AFI instruction for the Control/CompactLogix JSR rung – and maybe use just an XIC left in a ZERO status for the SLC/MicroLogix JSR rung ...

if my memory serves correctly – the LATCHED bit/box in the Control/CompactLogix system will now be reset to OFF – just like the SLC/MicroLogix ...

basic idea (again from memory) the Control/CompactLogix platform must have some "WAY" – some "PATH" – in order to find and scan the unused subroutine on PRE-SCAN – EVEN IF THAT PATH IS GUARANTEED TO BE FALSE ... the SLC/MicroLogix platform doesn't need any sort of path ... PRE-SCAN will go find that orphaned OTE instruction regardless ...

DISCLAIMER: I'm doing this by memory – and don't have time to double-check it – but I'd bet more than pocket change that I've got it right ...

closing out – this type of thing is one reason why I personally don't refer to "seal-in" rung constructions as "latched" rungs ... many people do that – but there is a BIG difference between how actual LATCHED/UNLATCHED rungs operate – and how "SEALED-IN" rungs operate ...
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Last edited by Ron Beaufort; December 14th, 2014 at 08:53 PM.
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Old December 14th, 2014, 08:47 PM   #7
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Quote:
Originally Posted by Ron Beaufort View Post
thanks ... good to know that someone has my back ... I'm working on putting together a little "dog and pony" show for Safety I/O in my "home" lab and I don't multitask too well when I'm this tired ...



I may have to correct this in the morning but here's the general idea ...

first let's start with an SLC or MicroLogix system ...

suppose that you're using a LATCH (OTL) instruction and an UNLATCH (OTU) instruction and that both rungs are FALSE ...

suppose that the bit/box has a status of ONE when you shut down the system ...

when the system powers back up again (go to run) the bit/box should still have a ONE status ... it "retains" its status is how this operation is usually described ...

but suppose that you add another rung even an UNconditional rung with an OTE instruction for the same bit address and that you place this rung in an UNUSED subroutine ... specifically, the subroutine has NO way to be executed ... no JSR no STI no DII no "NUTHIN" to tell the processor to scan/execute the OTE rung ...

(some programmers create a "scrap pile" subroutine and "park" unused rungs in it just in case they might need them later) ...

now when you power down and back up or go to program mode and then back to run mode (go to run) the LATCH bit will NOT retain its ON status ... specifically, PRE-SCAN will find that "UNUSED" OTE instruction and go write a ZERO into the bit/box ...

now for a ControlLogix or CompactLogix system ...

suppose that we set up the same test as before ...

now when you power down and back up or go to program mode and then back to run mode (go to run) the LATCH bit WILL retain its ON status ... specifically, PRE-SCAN operation will NOT find and execute that "UNUSED" subroutine ...

now add a JSR rung to "call" the unused subroutines in each of the systems and make both of the JSR rungs FALSE ... for example: use an AFI instruction for the Control/CompactLogix JSR rung and maybe use just an XIC left in a ZERO status for the SLC/MicroLogix JSR rung ...

if my memory serves correctly the LATCHED bit/box in the Control/CompactLogix system will now be reset to OFF just like the SLC/MicroLogix ...

basic idea (again from memory) the Control/CompactLogix platform must have "someway" some "PATH" - to find and scan the subroutine on PRE-SCAN EVEN IF THAT PATH IS GUARANTEED TO BE FALSE ...

DISCLAIMER: I'm dong this by memory and don't have time to double-check it but I'd bet more than pocket change that I've got it right ...

closing out this type of thing is why I personally don't refer to "seal-in" rung constructions as "latched" rungs ... many people do that but there is a BIG difference between how actual LATCHED/UNLATCHED rungs operate and how "SEALED-IN" rungs operate ...

Wow ! that's a gotcha for sure - I must test this asap - great heads-up, Ron..
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Old December 14th, 2014, 09:00 PM   #8
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I don't believe it is any different in Control/CompactLogix - the pre-scan simply resets any data-bits that are referenced by OTE instructions, and sets the storage bits for ONS instructions.
I think that you'll find that the Control/CompactLogix platforms (and the PLC-5) will indeed write a status of ONE into the bit/boxes for ONS instructions during the PRE-SCAN operation (go to run) ...

but ...

I also think that you'll find that the SLC/MicroLogix platforms will NOT affect the status of any OSR or ONS status bits during the PRE-SCAN operation ... specifically those OSR and ONS instructions are simply ignored during PRE-SCAN ...
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Old December 14th, 2014, 09:04 PM   #9
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Originally Posted by Ron Beaufort View Post
DISCLAIMER: I'm doing this by memory and don't have time to double-check it but I'd bet more than pocket change that I've got it right...
Thanks, and here's hoping your memory works better than mine has these last few years.
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Old December 14th, 2014, 09:13 PM   #10
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I must test this asap
well, I'm pretty sure that I've got it right - but it's been years since I've had to help debug a system with this particular "issue" ...

let us know if I've dropped a stitch ...
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Old December 14th, 2014, 10:02 PM   #11
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That was an interesting read Ron, thanks for that. Two things, first of all, in your signature, the output will simply always be on right, based on the way the PLC reads rungs. Second: My instructor is always complaining that our local school won't send him to your bootcamp. You are his hero .
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Old December 14th, 2014, 10:39 PM   #12
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first of all, in your signature, the output will simply always be on right, based on the way the PLC reads rungs.
Not a shakespeare fan then?
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Old December 14th, 2014, 10:46 PM   #13
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You are his hero
then he's never met me ...
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Old December 14th, 2014, 10:49 PM   #14
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Not a shakespeare fan then?
haha, "to be or not to be, that is the question." Silly me.

And no Ron, he has never met you, just a fan of your youtube vids.
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