I have a FX3U clone that I am failing to get a simple Structured Text example working on and would really appreciate some help. I created a simple ladder project that works exactly as expected, but have failed to get an equivalent ST program working. The program is very simple:
1. Sets DAC output 0 to full scale immediately after start up by checking for a rising edge on special register M8002 (I'm using this output as a 10v reference for a potentiometer).
2. On the rising edge of the 10ms clock register M8011 it samples analog input channel 1 (connected to potentiometer) and stores the value in D0.
3. On the falling edge of M8011, the value in D0 is written to analog output 1.
4. On each scan cycle the Y0 relay is set if the value in D0 is higher than half scale, otherwise cleared.
This is the ST program. The initialisation of DAC channel 0 works correctly, but the rising/falling edge detection of M8011 simply doesn't work, those code blocks are never entered. I have tried using LDP/LDF instructions (since this works on M8002) and also PLS/PLF instructions. Help!
1. Sets DAC output 0 to full scale immediately after start up by checking for a rising edge on special register M8002 (I'm using this output as a 10v reference for a potentiometer).
2. On the rising edge of the 10ms clock register M8011 it samples analog input channel 1 (connected to potentiometer) and stores the value in D0.
3. On the falling edge of M8011, the value in D0 is written to analog output 1.
4. On each scan cycle the Y0 relay is set if the value in D0 is higher than half scale, otherwise cleared.
This is the ST program. The initialisation of DAC channel 0 works correctly, but the rising/falling edge detection of M8011 simply doesn't work, those code blocks are never entered. I have tried using LDP/LDF instructions (since this works on M8002) and also PLS/PLF instructions. Help!
Code:
(* Check for start up condition *)
IF LDP(TRUE, M8002) THEN
(* Set DAC channel 0 to full scale output. THIS WORKS! *)
D0 := HFFF;
WR3A(TRUE, K0, K0, D0);
END_IF;
(* Check for clock rising edge *)
(* IF LDP(TRUE, M8011) THEN *)
PLS(M8011, M0);
IF M0 THEN
(* Read ADC channel 1. NEVER GETS HERE! *)
RD3A(TRUE, K0, K1, D1);
END_IF;
(* Check for clock falling edge *)
(* IF LDF(TRUE, M8011) THEN *)
PLF(M8011, M1);
IF M1 THEN
(* Write ADC result to DAC channel 1. NEVER GETS HERE! *)
WR3A(TRUE, K0, K1, D1);
END_IF;
(* Set/Clear Y0 output depending on ADC channel 1 value *)
Y0 := (WORD_TO_INT(D1) > H7FF);