thanks for the link, i don't think i saw it before...
I haven't seen any proof or confirmation yet that disabling
counter reset logic still results in random counter resets.
one of earlier posts says that 'problem started happening'
indicating that it was working for some time without issues
but the thread you linked to is only few days old so this
can't be true. maybe occurance of unwanted errors just happened
to be lower or masked by other problems (we had a long weekend
here too so this couldn't be running that much).
things is saw in sample logic bug me a bit too and make me
wonder if everything else is sound there (haven't seen whole
plc program yet either)
for example i'm not sure why reset of a high speed counter card
in this case has to be variable (anything less than a second)!?
if long reset is required for example to trigger that relay output,
then make it at least repeatable. short reset pulses will not
even move realy becasue of slow relay response (it's mechanical device).
if reset has to be done this way i would like to see at least
a seal with T4:49/TT bit around T4:50/DN bit in rung 4 to keep
T4:49 timer running every time it's triggered until it's done timing.
I checked the counter card configuration (content of N9 file) and
it is usable, but I would suggest reseting N9:1/11 (change counter mode
to "Pulse count with internal direction") and changing reset mode to
Soft reset (set N9:1/7 and clear N9:1/6).
This way counter will only receive pulses from that photoeye,
everything else (other external inputs like reset, channel B etc.) will be
ignored including possible erroneous pulses they might introduce
if subject to noise or faulty wiring. (not shielded wiring to
high speed counter card is also faulty wiring!).
Since N9:1/3 is zero, it will only count up. Card itself should be quite
imune to noise (I've been using HSCE2 most of the time, don't even remember
last HSCE1...), it's the wiring that requires scrutiny.
Reseting can now be done on one shot by pulsing soft reset bit
(note that i said one shot pulse and not anything longer).
This makes it easier to catch unwanted resets, if reset ever happens
(check if I:e.0/12 is high) when PLC program didn't request it, set the
alarm bit.
Also set another alarm bit if I:e.0/13 (overflow) is ever set.
Next thing, I would evaluate those two inputs used to reset counter.
Do they maybe come randomly on (are we really sure there are no false
triggers? how do we check for that?)
may reset not be with you...