Need help with basic ladder logic.

XIO,

Remember Ron Beaufort's "big hint", post #12. Things do not happen instantly with a PLC. And they scan the ladder top to bottom. This makes PLC's like a timer. But unlike a timer the "timing" is in sync with the plc.
logicalflipflopnoaddresses.jpg

This should work on your PLC. Can you tell me how it works?

If you put rung #2 first it won't work. Why?
 
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Ron Beaufort said:


it might not sound like a big difference but the way you said it originally sounds like Yoda-Talk ... sort of like “train this one I cannot - patience he has none” ...


OMG thats funny !
 
milldrone said:
XIO,

Remember Ron Beaufort's "big hint", post #12. Things do not happen instantly with a PLC. And they scan the ladder top to bottom. This makes PLC's like a timer. But unlike a timer the "timing" is in sync with the plc.
logicalflipflopnoaddresses.jpg

This should work on your PLC. Can you tell me how it works?

If you put rung #2 first it won't work. Why?


I'm a noob too so I want to take a shot at it.

During the scan that sees the input high, rung 1 goes true and rung 2 goes true.

Near the end of the same scan the output goes high and the internal bit goes high.

When you take your finger off the button, during the scan that sees the input low, the output is sealed through the branch and the internal bit goes low.

When you press the button again, the input on the branch goes high, breaking branch-rung continuity, but the internal bit on the nested branch holds the output true until you take your finger off the button, and then the output goes low because the internal bit went low.

Did I get it ??
 
milldrone said:
ascot01,

Yes you did. Now why does it not work when you reverse the rung order?

Not a wild guess, but a guess nevertheless:

With the rungs in reverse order, and the output off, as the scan looks at all instances of the input, from left to right - top to bottom, the last one it remembers and uses to update the input register, is the XIO on the branched rung.

So, the input register gets a '0' instead of a '1'.

????
 
XIO


I am woth you here. Sometimes you just need simple help to a simple problem.

Couple of ways to do this GX Developer.

I would look up the ALT command in the manual. This typical ALTernates and out out based on the input. Depending on your exact hardware you may or may not need to use edge instructions.

Code could be as simple as:

LD XO - this is a normally open load, when you press button X0 turns on
ALT YO - this is helplful instruction that Mitsubishi offers to do this very common task. You could write this yourself, but that is why they build it for you.

The one change may be to switch from LD X) to LDP XO. the LDP is a load pulse, or rising edge. This will only trigger the ALT commands when the state of XO input goes from off to on, this will prevent your output changing state while you hold in the button. Without knowing which PLC you are using exactly, I think this is built into the ALT command, but one of the other should get you going.

Chuck
 
Chuck, XIO did mention LADDER, if he needed an explanation in Mnemonic or ST then that explanation would help, lets keep it to the point, XI0 is new to this amazing technology, there are to many CONTROL FREEKS out there guys. Never Stop Learning
 
Not a wild guess, but a guess nevertheless:

With the rungs in reverse order, and the output off, as the scan looks at all instances of the input, from left to right - top to bottom, the last one it remembers and uses to update the input register, is the XIO on the branched rung.

So, the input register gets a '0' instead of a '1'.
Roy, if you have a PLC Simulator program available, you can set it to Single Scan and test your guess. I did, and this is what I saw:

With Rung 2 moved above Rung 1, then doing a STEP Single Scan: (1) When Input is TRUE, Internal Address goes ON. (2)In Rung 1, because Internal Address is now ON, the Internal Address XIO on the top branch keeps the Output from going ON. (3) Rung 1 branch is also FALSE because Output is OFF.
 
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Davo_Prog said:
Chuck, XIO did mention LADDER, if he needed an explanation in Mnemonic or ST then that explanation would help, lets keep it to the point, XI0 is new to this amazing technology, there are to many CONTROL FREEKS out there guys. Never Stop Learning

|
|--|X0|----------|ALT M0|-
|
|--|M0|--------------|Y0|-
|
 
Lancie1 said:
Roy, if you have a PLC Simulator program available, you can set it to Single Scan and test your guess. I did, and this is what I saw:

With Rung 2 moved above Rung 1, then doing a STEP Single Scan: (1) When Input is TRUE, Internal Address goes ON. (2)In Rung 1, because Internal Address is now ON, the Internal Address XIO on the top branch keeps the Output from going ON. (3) Rung 1 branch is also FALSE because Output is OFF.

I see now, makes sense thanks. I'll get that into my LogixPro and try it too
 
rsdoran said:
I have several examples on my site (signature) but I have a feeling you are bulldogging this and have not read any tutorials like the one provided on this site. The tutorials may not offer everything but will give you a better understanding of basic instructions and how a plc perfoms them.

You are wrong on this one. I am doing my best to learn. You have to understand that I am new to PLCs. I have read the FX manual from mitsubishi for the basic operations, I have also read other sites on the internet but there are still basic ideas that confuse me.
 
Lancie1 said:
Roy, if you have a PLC Simulator program available, you can set it to Single Scan and test your guess. I did, and this is what I saw:

With Rung 2 moved above Rung 1, then doing a STEP Single Scan: (1) When Input is TRUE, Internal Address goes ON. (2)In Rung 1, because Internal Address is now ON, the Internal Address XIO on the top branch keeps the Output from going ON. (3) Rung 1 branch is also FALSE because Output is OFF.[/

OK I did that and it seems clear now.

With the rungs reversed, the scan that sees the input go high sets the internal bit high.

After that scan, there's no continuity on the output rung because the XIO (internal bit) is False and also because the XIO (input bit) on the branch is False.

Is that right??
 

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