Figuring out some Timer Instruction Issues - Micrologix 1200

[mike64b]

EDIT: I think I just noticed I never cleared B3:4/11 after the timer completes. DOH, thats probably the cause, thanks anyways!



Hi guys, I've got a micrologix 1200 that I'm trying to get some timer instructions to work with..The 2 ladder rungs below are having some issues:

First I set B3:4/11 to "1", so it should go through and count the timer. If the done bit is not set, it RET's (which then goes to the end of the program to start a new cycle). Once the done bit is set, we latch an output solenoid and set the B3:4/13 toggle to go to the next rung (after a new cycle) and wait another 3 seconds and latch another solenoid.

Now when running, I see it get to setting B3:4/11 but it never finishes the first timer as far as I can tell. I never see B3:4/11 get cleared... So Is my syntax wrong here?

Thanks

 

[OkiePC]

What's up with the early conditional RETURNs?

 

[mike64b]

OkiePC, well technically I know it's not good programming practice, but I like to use this method since it's similar to how writing in C goes... Basically the timer counts, if it's not done, we RET out and skip to the end of the program, start a new cycle, go and do a new count, check if finished, repeat...

I know I could also just put the RET's at the end of the program file so that the timer counts, check if its finished, if its not it just goes to the next rung which would be the RET's, but this seems clearer to me..

 

[Tharon]

I'd say the use of Returns stems from a lack of understanding of how the PLC works.

You also have one timer address being used on two different timers.

 

[mike64b]

I'd say the use of Returns stems from a lack of understanding of how the PLC works.

You also have one timer address being used on two different timers.

Can you give a reasoning as to what will go WRONG with using this method? I know its simpler to just use conditional logic to skip over lines in the PLC but I like using this method because it's clearer to me. AFAIK this will cause no problems assuming I keep in mind that I have these conditional RET's so I don't have problems with code elsewhere.

Additionally, perhaps I am mistaken but since only one timer is used at a time, I thought I could use the same timer file..though it's been a while so I should probably go review timer usage.

 

[daba]

This has to be one of the most unusual ways of sequencing 2 solenoids I have ever seen.

From the code you posted I assume you want Solenoid 2 to energise 3 seconds after B3:4/11 comes on, then Solenoid 1 energises 3 seconds later.

We can't see when the solenoids are turned off, so I'll assume they go off later. There are far better (more concise, more understandable, more robust, etc) ways to achieve this.

If it were me, I would make the WHOLE cycle using 1 timer only, and inspect the .ACC value with Comparison instructions, LES, LEQ, GRT, GEQ, or preferably LIM, to determine when the solenoids should be ON.

I could also suggest that you look at the SQO instruction which would appear to be capable of doing all that you want...

 

[daba]

Additionally, perhaps I am mistaken but since only one timer is used at a time, I thought I could use the same timer file..though it's been a while so I should probably go review timer usage.

You are mistaken. A-B PLC timers are not timers at all. The timer data-types are just memories for data, the actual timing is done by comparison with the PLCs internal clock.

You cannot "re-use" them.

 

[mike64b]

DABA thanks, I can't believe I didn't think about the ACC value. You are right, a single timer and inspecting the ACC value will be much simpler, I'm still convinced my method works(can't try it at the moment) but I'll be switching it to use 1 timer.

As for SQO's, I looked into them a while back but I basically implemented my own sequencer which was easier to understand IMO.

 

[OkiePC]

OkiePC, well technically I know it's not good programming practice, but I like to use this method since it's similar to how writing in C goes...

Forget how C goes for a second, and keep a perfect udnerstanding and adherence to the PLC scan cycle or you will be forever band-aiding your c-simulator...



I have had to follow up and re write code written by very intelligent and well meaning C programmers more than once, and untangling the mess of their attempts at flow control was the reason for my headbanging emoticons...

Conditional returns is more than bad practice in ladder logic. It is simply wrong. There are wrong ways to program PLCs, and this is an example...

Sorry, I know many people believe there's no wrong way to write code as long as it works, but I disagree.

Paul

Proof that it is wrong:

The conditional return execution time far exceeds that of quite a few (dozen?) bit examine instructions which examine false...it is there fore a detriment to processor efficiency.

It makes output (data-destructive) instructions conditionally skipped (go through all those unintended consequences every time you edit anything past the "possible" early return).

It will **** off any PLC programmer or electrician who ever has to understand it in order to make changes or troubleshoot it.

 

[Lancie1]

Basically the timer counts, if it's not done, we RET out and skip to the end of the program, start a new cycle, go and do a new count, check if finished, repeat...

No, RET does not skip to the end of the program. It "returns" to the instruction immediately below the calling instruction (JSR)

RET (Return): This output instruction marks the end of subroutine execution or the end of the subroutine file. It causes the processor to resume execution in the main program file at the instruction following the JSR instruction where it exited the program.
Rockwell Software

The closest instruction that does what you described would be the TND (Temporary End) instruction. However I do not recommend that you continue with this screwy method.

Suggestion: Describe in written English sentences how you want these solenoids to operate, and some expert here will help you find the best way to do it using RSLogix. Forget about using RET for this job!

 

[mike64b]

No, RET does not skip to the end of the program. It "returns" to the instruction immediately below the calling instruction (JSR)
The closest instruction that does what you described would be the TND (Temporary End) instruction. However I do not recommend that you continue with this screwy method.

I meant in my program, the RET leaves the current program file and goes to the end, I didn't mean to say that the RET instruction does this, just in my program the way things are setup when it returns out it starts a new cycle.

 

[daba]

Sorry Mike, IMHO I don't believe your method is "easier to understand", on the basis that you didn't get it working, and made incorrect assumptions about data-table usage.

For a simple sequencing application like you described, the SQO was made for the job.

When I started in PLC control systems over 25 years ago, the guy who "mentored" me gave me lots of useful advice. He called them "rules" but they are not rules by any means....

Rule #15 : Let the processor scan all of the code in a file all of the time. At some point in time you will puzzling over a piece of code and wondering why it isn't working. If it's not being scanned, it won't work.

Rule #16 : Don't use JMP/LBL unless you HAVE TO. This ties in with rule #15.

Rule #17 : Don't use MCR zones unless you HAVE TO. This ties in with rule #15.

Rule #18 : Don't make your code "position dependant". This ties in with rule #15.

etc.

 

[Lancie1]

Rule #15 : Let the processor scan all of the code in a file all of the time.

Right on, mate.

PLCs were originally designed to replace relays. Relay logic wiring is where all relays are "online" and "scanned" all the time to be either on or off, with no beginning point and no end point.

Mike, If your PLC logic program deviates very far from the premise of all rungs being continuously scanned, you are asking for trouble. There are exceptions, but those are best done when you know a little more.

 

[OkiePC]

All PLC programmers should have to build five step sequencers on din-rail mounted, plug in relay logic with electronic timers and counters before they get the laptops out...

But as soon as they start looking at PLCs, they need to own a complete understanding of the scan cycle, the fact that it can vary among manufacturers, and how I/O memory is updated...why 1500 rungs that execute false is fine and dandy...etc...etc...

 

[Tharon]

All PLC programmers should have to build five step sequencers in relay logic with timers and counters before they get the laptops out.

My first PLC course in college had big relay boards and we had to wiring up timers, relays, sequences, etc.

Then after were learned that, the instructor said "Here's a PLC, watch how much easier it is to do this and make changes".