Counter (CTU) spontaneously resets - Expert opinion requested

... but the counter instruction, by design, rarely needs one ahead of it.

I would even go so far as to say that a one-shot instruction in front of a counter is absolutely pointless, the counter logic itself performs that function, using it's internal .CU memory bit. An external one-shot cannot affect how the counter counts in any way (unless you are resetting the one-shot's memory bit elsewhere).

Just about the only "trick" you can do with a counter is to make it count every time the rung is scanned with the rung conditions in permanently true, and that involves resetting the .CU bitwith an OTU instruction. The next time the rung is scanned, it "sees" the rung is true, with its internal memory bit (.CU) off, and counts up. The same applies to the CTD instruction and the .CD memory bit.
 
Should I simply replace the [XIO C5:0/CU] with an OSR?

if it worked OK for years - and then messed up ONCE - then personally I wouldn't change anything UNTIL - and UNLESS - I fully understood EVERYTHING about how the rest of the program works ...
 
actually in some cases there is a valid reason to put a one-shot in front of a CTU ... I've seen the technique being used in a few programs that I've run across over the years ...

http://www.plctalk.net/qanda/showthread.php?p=137158&postcount=15

the last figure of the post shows an example ...

there are other ways of correcting for the "false count on a reset" problem - but some programmers just use the one-shot approach ...
 
Let's just go off what we do know.


1) Since it is controlling a sequencer we can say with a reasonable degree of certaintly that it should NOT be counting anywhere near as fast as every other scan.

2) It WILL "run away" in all instances where the RLO prior to the C5:0/CU remains true. (Assuming this code is not being executed in a conditional subroutine and assuming the ACC is not being forced somewhere else)

3) Since the B3:5/1 is a manual pause for the HMI, it is reasonable to believe that the problem is not related to that and assume for our purposes that it always evaluates true. (Otherwise the OP hopefully would have mentioned that the problem only occurs when they go in and out of pause).

4) B3:4/9 MUST be on all the time during the entire sequence or the counter will just get reset before it makes any progress. Ron's point about the reset when going into run mode is taken, but again I would have expected the OP to have made mention whether they were putting the system in and out of run mode or cycling power when the issue is occuring.

That pretty much leaves the comparator.
So the next question is, what is this comparator supposed to do, because based on the descriptions it seems misplaced. Count at all times unless the counter ACC is negative? Well, as far as I knew negative values are not allowed in the ACC of a timer (I even tried and it slapped my hand). So it would seem that this would be on ALL the time with N11:0 set to 0.

Can the OP confirm that N11:0 has always been 0?

Even so, what is the purpose of N11:0 other than to "pause" the sequencer from counting until the timer has been running for a minimum time. In which case as soon as that comparator is satisfied the counter will again start free-wheeling.

With all that being said, the only things that make sense given the information we have been is that this code is probably being executed conditionally whether in a separate subroutine or is being jumped around until the step conditions are satisfied.

This might possibly explain why the C5:0/CU is there. If this code is conditionally executed as I suspect then based on how the code was written it would not be able to properly detect transitions. As soon as the code is scanned again it would never actually count up unless the conditions ahead of it were seen to transition from false to true WHILE that code was executing. So this network forces it to count up at least once so long as all the previous three conditions evaluate true.

That's IF the problem is caused by a free running counter.

So if it is a free-wheeling counter issue then it probably has to do with the code that makes sure this is only scanned conditionally.


The OP also mentions the
"N" data table that holds the "reset" bit

Holds the reset bit for what? Is there a reset on the counter somewhere else? Witholding information is obstruction of justice.

So the counter getting prematurely reset somewhere else is still a reasonable possiblity.

Perhaps the OP could make a screen shot of the cross reference on C5:0 as well as a screen shot of the T4:21 timer code?

Also, what does this comment mean
My first thought was that the values in N11:0 were "zeroed" out, but they're not
N11:0 is ONE value. When you say "the values zeroed out" are you referring to the bits of N11:0?

A screen shot of a cross reference of N11:0 might not be bad idea either.

VALVE%20SEQUENCER%20LOGIC.jpg
 
IMPORTANT! ... this post is NOT meant to be argumentative in any way ... I'm just trying to help nail down the problem ...

from DamianInRochester:

Ron's point about the reset when going into run mode is taken, but again I would have expected the OP to have made mention whether they were putting the system in and out of run mode or cycling power when the issue is occuring.

going back to Post #1 ... the OP asked:

Could a faulty output card cause a PLC reset that would restart the counter?

now I'll admit that I haven't had time to really follow everything involved in this thread – so OP please correct anything that I've got wrong ...

BUT ... I *THINK* that the problem has only happened ONCE ...

and I've got a hunch that when the OP asked about a "PLC reset" that he implied that the processor was (in one way or another) taken through either a power cycle – or had to be reset from a "fault" condition ... either one of those actions would certainly have accounted for the "GO-TO-RUN" operation that I mentioned earlier ...

so if the OP was initially concerned about a "faulty output card" MAYBE the card was replaced during troubleshooting – and if that happened, then it's a pretty sure bet that the processor had to be taken through some sort of "GO-TO-RUN" operation ...

DISCLAIMER:

I'll freely admit that the scenario that I've brought up is an unlikely candidate – BUT – if all else fails, we still need to consider ALL possible root causes of the problem – regardless of how unlikely ... over the years I've helped debug many programs that worked PERFECTLY under normal day-to-day operations – but then, for some mysterious reason they would sometimes "act up" after a "GO-TO-RUN" operation ... things like the issue I've brought up here are usually the culprit ...

the point: many programmers are content to get their systems running OK under "normal" conditions – but then they fail to consider how the program will react when it's "started up" in some NON-normal situation ...

so ...

I suggest that we continue to explore ALL of the other possible culprits first – and put my "GO-TO-RUN-PRESCAN" idea on the back burner ...

and personally I'd still like to see the entire program file ... without that, most of what we're doing here is pure speculation ...

party on ...
 

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